MAX1302 Datasheet, PDF (5/31 Pages) Maxim Integrated Products – 8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs

8-/4-Channel, ±V_REF Multirange Inputs,
Serial 16-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD1 = AV_DD2 = DV_DD = DV_DDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f_CLK = 3.5MHz (50% duty cycle),
external clock mode, V_REF = 4.096V (external reference operation), REFCAP = AV_DD1, maximum single-ended bipolar input range
(±V_REF), C_DOUT = 50pF, C_SSTRB = 50pF, T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
Preamplifier Supply Voltage
Digital I/O Supply Voltage
AV_DD1 Supply Current
SYMBOL
AV_DD2
DV_DDO
CONDITIONS
I_AVDD1
External clock mode,
external acquisition
mode, or internal
clock mode
Internal reference
External reference
MIN TYP MAX UNITS
4.75
5.25
V
2.70
5.25
V
3
3.5
mA
2.5
3
DV_DD Supply Current
I_DVDD
External clock mode, external acquisition
mode, or internal clock mode
AV_DD2 Supply Current
I_AVDD2
External clock mode, external acquisition
mode, or internal clock mode
DV_DDO Supply Current
I_DVDDO
External clock mode, external acquisition
mode, or internal clock mode
Total Supply Current
Partial power-down mode
Full power-down mode
Power-Supply Rejection Ratio
PSRR All analog input ranges
TIMING CHARACTERISTICS (Figures 15 and 16)
External clock mode
SCLK Period
t_CP
External acquisition mode
Internal clock mode
External clock mode
SCLK High Pulse Width (Note 5)
t_CH
External acquisition mode
Internal clock mode
External clock mode
SCLK Low Pulse Width (Note 5)
t_CL
External acquisition mode
Internal clock mode
DIN to SCLK Setup
t_DS
DIN to SCLK Hold
t_DH
SCLK Fall to DOUT Valid
t_DO
CS Fall to DOUT Enable
t_DV
0.9
2
mA
17.5
25
mA
0.2
1
mA
1.3
mA
2
µA
±0.5
LSB
272
62
228
62
µs
100
83
109
92
ns
40
109
92
ns
40
40
ns
0
ns
40
ns
40
ns
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