MAX1246 Datasheet, PDF (5/24 Pages) Maxim Integrated Products – +2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16

+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
TIMING CHARACTERISTICS
(V_DD = +2.7V to +3.6V (MAX1246); V_DD = +2.7V to +5.25V (MAX1247); T_A = T_MIN to T_MAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
t_ACQ
t_DS
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSH
t_CH
t_CL
t_SSTRB
t_SDV
t_STR
t_SCK
Figure 1
Figure 1
Figure 2
MAX124_ _C/E
FMigAuXr1e214_ _M
Figure 1
External clock mode only, Figure 1
External clock mode only, Figure 2
Internal clock mode only (Note 7)
1.5
µs
100
ns
0
ns
20
200
ns
20
240
240
ns
240
ns
100
ns
0
ns
200
ns
200
ns
240
ns
240
ns
240
ns
0
ns
Note 1: Tested at V_DD = 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX1246—internal reference, offset nulled; MAX1247—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V_DD.
Note 7: Guaranteed by design. Not subject to production testing.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
| | ^{Note 10: Measured as V}FS^{(2.7V) - V}FS^(VDD, MAX^{) .}
__________________________________________Typical Operating Characteristics
(V_DD = 3.0V, VREF = 2.500V, f_SCLK = 2.0MHz, C_LOAD = 20pF, T_A = +25°C, unless otherwise noted.)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
INTEGRAL NONLINEARITY
vs. CODE
1024
2048
3072
4096
CODE
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
2.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX1246
MAX1247
2.75 3.25 3.75 4.25 4.75 5.25
V_DD (V)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.50
0.45 ^{VDD = 2.7V}
0.40
0.35
0.30
MAX1246
0.25
0.20
0.15
MAX1247
0.10
0.05
0.00
-60
-20 20
60 100 140
TEMPERATURE (°C)
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