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MAX107 Datasheet, PDF (5/21 Pages) Maxim Integrated Products – Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK = 401.408MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C)
PARAMETER
DREADY Duty Cycle
LVDS Output Rise-Time
LVDS Output Fall-Time
LVDS Differential Skew
DREADY Rise-Time
DREADY Fall-Time
Primary Port Pipeline Delay
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
(Notes 5, 13)
47
53
%
tRDATA 20% to 80% (Notes 5, 13)
200
500
ps
tFDATA 20% to 80% (Notes 5, 13)
200
500
ps
Any differential pair
<65
tSKEW1
Any two LVDS output signals except DREADY
<100
ps
tRDREADY
tFDREADY
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
200
500
ps
200
500
ps
tPDP
5
Clock
Cycles
Auxiliary Port Pipeline Delay
tPDA
6
Clock
Cycles
Note 1: INL and DNL is measured using a sine-histogram method.
Note 2: Input offset is the voltage required to cause a transition between codes 0 and -1.
Note 3: Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input voltage
level does not matter.
Note 4: The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algo
rithm (e.g. FFT).
Note 5: Guaranteed by design and characterization.
Note 6: Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-mode
voltage expressed in dB.
Note 7: Measured with analog power supplies tied to the same potential.
Note 8: Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
Note 9: The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Note 10: Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Note 11: Harmonic distortion components two through five are included in the total harmonic distortion specification.
Note 12: Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of fIN = 124.999 MHz.
Note 13: Measured with a differential probe, 1pF capacitance.
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