DS1859 Datasheet, PDF (5/28 Pages) Maxim Integrated Products – Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors

Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Note 10: After this period, the first clock pulse is generated.
Note 11: The maximum t_HD:DAT only has to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.
Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the V_{IH MIN} of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 13: C_B—total capacitance of one bus line, timing referenced to 0.9 x V_CC and 0.1 x V_CC.
Note 14: Guaranteed by design.
Typical Operating Characteristics
(V_CC = 5.0V, T_A = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
720
SDA = SCL = V_CC
680
640
600
560
520
-40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
RESISTANCE vs. SETTING
20
20kΩ VERSION
15
10
5
0
0
50 100 150 200 250
SETTING (DEC)
SUPPLY CURRENT vs. VOLTAGE
700
SDA = SCL = V_CC
650
600
550
500
450
400
3.0 3.5 4.0 4.5 5.0 5.5
VOLTAGE (V)
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
760
SDA = V_CC
720
680
640
600
560
0
100
200
300
400
SCL FREQUENCY (kHz)
RESISTANCE vs. SETTING
60
50kΩ VERSION
50
40
30
20
10
0
0
50 100 150 200 250
SETTING (DEC)
RESISTOR 0 INL (LSB)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
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