MAX5980 Datasheet, PDF (46/49 Pages) Maxim Integrated Products – Quad, IEEE 802.3at/af PSE Controller

Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Port Current-Limit Register
(R48h, R4Dh, R52h, and R57h)
The Port Current-Limit registers (Table 41) are used to set
the current-limit SENSE_ voltage threshold for the corre-
sponding port. On a power-up or after a reset condition,
these registers are set to a default value of 80h. Bit 7 is
hardwired to 1, while bits 5 to 0 are hardwired to 0. ILIM_
(bit 6) is set to 0 for a Class 0–3 PD, and to 1 for a Class
4 or 5 PD. The state of ILIM and the classification result
(in the case of Class 5) determine the current limit (see
the Electrical Characteristics table, VSU_LIM for details).
Port High-Power Status Register
(R49h, R4Eh, R53h, and R58h)
The Port High-Power Status registers (Table 42) are
used to external FET failures and successful 2-event
classification results. On a power-up or after a reset
condition, these registers are set to a default value of
00h. FET_BAD_ is set to 1 if the port is powered, there
is no current-limit condition, and VOUT_ - VEE > 2V.
PONG_PD_ is set to 1 every time a successful 2-event
classification occurs on the corresponding port.
Table 40. Port Overcurrent Register
ADDRESS = 47h, 4Ch, 51h, 56h
SYMBOL
BIT NO. TYPE
RDIS_
7
R/W
CUT_RNG_
6
R/W
5
R/W
4
R/W
ICUT_[5:0]
3
R/W
2
R/W
1
R/W
0
R/W
DESCRIPTION
Sets the current-sense scale on the corresponding port; always set to 1
ICUT is doubled when set to 0
Sets the overcurrent SENSE_ voltage threshold (VCUT) for the corresponding port
Table 41. Port Current-Limit Register
ADDRESS = 48h, 4Dh, 52h, 57h
SYMBOL
BIT NO. TYPE
1
7
—
ILIM_
6
R/W
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
—
DESCRIPTION
Hardwired to 1
Current-limit setting for the corresponding port
Hardwired to 0
Table 42. Port High-Power Status Register
ADDRESS = 49h, 4Eh, 53h, 58h
SYMBOL
BIT NO. TYPE
Reserved
7
R/W
Reserved
6
R/W
Reserved
5
R/W
Reserved
4
R/W
Reserved
3
R/W
Reserved
2
R/W
FET_BAD_
1
R/W
PONG_PD_
0
R/W
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Set to 1 if a FET failure is detected on the corresponding port
Set to 1 when a 2-event classification has occurred
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