MAX11300 Datasheet, PDF (45/54 Pages) Maxim Integrated Products – Up to 20 General-Purpose Digital I/Os

MAX11300
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Port Configuration Registers (Read/Write)(continued)
BIT
FIELD NAME
DESCRIPTION
• 0011: Mode 3 - Register-driven digital output with DAC-controlled level, GPO (Figure 9)
• The port is configured as a GPO driven by the corresponding GPODAT register bit. The
logic one level is set by the DAC data register of that port.
• The port’s DAC data register needs to be set first. It may require up to 1ms for the port
to be ready to produce the desired logic one level. At that point, the port can be set in
mode 3. The logic level at the port is then controlled by the corresponding GPODAT
register bit.
• 0100: Mode 4 - Unidirectional path output with DAC-controlled level, GPO (Figure 10)
• The port is configured as a GPO forming the output of a unidirectional level translator
path. The input port of that path is specified by the functional parameter, ASSOCIATED
PORT, and that port must be separately configured in GPI mode. The port’s DAC data
register defines the logic one level. The data received by the GPI-configured port is
transmitted by this port configured in mode 4.
• The data from the associated GPI-configured port can be inverted by asserting the
functional parameter INV.
• Multiple ports configured in mode 4 can refer to the same GPI-configured port through
the functional parameter, ASSOCIATED PORT. Therefore, one GPI-configured port can
transmit its data to multiple ports configured in mode 4.
• To avoid false interrupts and unexpected activity at the port configured in mode 4, the
GPI port must be configured before this port is configured in mode 4.
• Functional parameters to be set: INV, ASSOCIATED PORT
• 0101: Mode 5 - Analog output for DAC (Figure 6)
• The port’s DAC data register must be set for the desired voltage at the port. It may take
up to 1ms for the port to reflect the data written in the DAC data register.
• Functional parameters to be set: RANGE (codes 001, 010, and 011 apply to this mode).
• 0110: Mode 6 - Analog output for DAC with ADC monitoring (Figure 7)
• In addition to the functionality of mode 5, the port is sampled by the ADC. The result of
the ADC conversion is stored in the port’s ADC data register. The host can access that
register to monitor the voltage at the port.
• When the ADC input voltage range is set from 0V to 2.5V, (RANGE = 100 or 110), the
DAC data register value must be limited to the range of values corresponding to 0V to
2.5V at the port. Internally, the DAC data register value is clipped, so that the PIXI port
voltage is contained within a range from 0V to 5V to prevent device damage.
• Functional parameters to be set: AVR, RANGE
• 0111: Mode 7 - Positive analog input to single-ended ADC (Figure 3)
• The port is configured as a single-ended ADC input.
• Functional parameters to be set: AVR, RANGE, # OF SAMPLES
• 1000: Mode 8 - Positive analog input to differential ADC (Figure 4)
• The port is configured as a differential ADC positive input.
• Functional parameters to be set: AVR, RANGE, # OF SAMPLES, ASSOCIATED PORT
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