DS26522 Datasheet, PDF (43/258 Pages) Maxim Integrated Products – Dual T1/E1/J1 Transceiver

DS26522 Dual T1/E1/J1 Transceiver
8.9.3 T1 Transmit Synchronizer
The DS26522 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries
within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit
synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are
located in the TSYNCC register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a loss-of-frame
synchronization has occurred. The real-time bit (LOF) is also provided to indicate when the synchronizer is
searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB.
Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the
recovered frame-sync pulse will be output on this signal. The recovered CRC-4 multiframe sync pulse is output if
enabled with TIOCR.0 (TSM = 1).
Other key points concerning the E1 transmit synchronizer:
1) The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes.
2) The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not verify
CRC-4 codewords.
The Tx synchronizer cannot search for the CAS multiframe. Table 8-10 shows the registers related to the transmit
synchronizer.
Table 8-10. Registers Related to the Transmit Synchronizer
REGISTER
FRAMER
ADDRESSES
FUNCTION
Transmit Synchronizer Control Register
(TSYNCC)
18Eh
Resynchronization control for the transmit
synchronizer.
Transmit Control Register 3 (TCR3)
183h
TFM bit selects between D4 and ESF for the
transmit synchronizer.
Transmit Latched Status Register 3
(TLS3)
Transmit Interrupt Mask Register 3
(TIM3)
Transmit I/O Configuration Register
(TIOCR)
192h
1A2h
184h
Provides latched status for the transmit
synchronizer.
Provides mask bits for the TLS3 status.
TSYNC should be set as an output.
Note: The addresses shown are for Framer 1. The address for Framer 2 can be calculated by adding 200 hex to the framer address.
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