MAX11800 Datasheet, PDF (41/56 Pages) Maxim Integrated Products – Low-Power, Ultra-Small Resistive Touch-Screen Controllers with I2C/SPI Interface

Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I²C/SPI Interface
I²C Configuration or Result Register Read
(MAX11801/MAX11803)
The read sequence does not limit the number of bytes to
be read. The internal register counter keeps increment-
ing as additional bytes are requested. The first byte out
is Reg(N) as shown in Figure 24. The next byte out is
Reg(N+1). The next byte out is Reg(N+2), and so on.
The programmer needs to keep track of the incremented
register address. Acknowledge pulses from the master
are not required to autoincrement the internal register
location. The internal register location updates on each
byte. See the Command and Register Map section for
details governing the incrementing of register addresses.
The autoincrement reads only the X, Y, Z1, Z2, and
AUX result registers preventing inadvertent readback of
unrelated or reserved data locations. For example, if
beginning at the XMSB register, a user can cycle
through the XLSB register to the YMSB register and so
forth up to the AUXLSB register. The MAX11801/
MAX11803 do not autoincrement beyond the AUXLSB
register. If clock cycles continue to be given, the
AUXLSB register readback is repeated.
The FIFO (MAX11801) register does not autoincrement,
which allows multiple readbacks of the same location.
This allows the access to multiple FIFO memory blocks
with a single read operation. When reading back FIFO
registers, data management is handled in blocks not
bytes. As a result, when an I²C read operation supplies
at least one cycle for readback of the first byte of a FIFO
block, the entire block is marked as read. This is regard-
less of whether the block or even byte readback is run
to completion.
• Streamlined I²C Read Operations (MAX11801/
MAX11803)
The MAX11801/MAX11803 support several streamlined
readback behavior to significantly improve data transfer
efficiency. Using the streamlined readback sequence
shown in Figure 25, data readback can commence fol-
lowing an assumed progression. Disable the stream-
lined readback feature to allow full readback sequence.
• Resumed Read Operations (MAX11801/
MAX11803)
When readback operations are suspended and later
resume from the current (incremented) register loca-
tion, it is not necessary to supply the initial device
address and register start sequence. Begin the read-
back portion of the command following the streamlined
sequence shown in Figure 25 to allow more efficient
data transfer.
For example, if the user accesses the FIFO register
(MAX11801), which does not autoincrement, and reads
several observations and then stops and resumes the
readback operation at a later time, the user only needs
to issue the streamlined readback sequence to contin-
ue to gather observations from the FIFO. Once the
device is placed in autonomous mode, the user only
needs to issue the full readback sequence once for the
initial FIFO access. Then streamlined read access to
the device resumes at the FIFO location, unless an
intervening command is issued as shown in Figure 25.
Similarly, when reading back result registers, begin with
XMSB and autoincrement to XLSB, then stop. When
readback resumes by the issuance of the streamlined
readback sequence, data readback commences from
the YMSB location.
START
SDA
SCL
WRITE ADDRESS
BYTE 1: DEVICE ADDRESS
WRITE REGISTER START NUMBER
BYTE 2: FIRST REG NUMBER = N
REPEATED
WRITE ADDRESS
START BYTE 3: DEVICE ADDRESS
READ DATA
BYTE 4: REG(N)[7:0] DATA
1 0 0 1 0 A1 A0 W A N N N N N N N N A
1 0 0 1 0 A1 A0 R A D D D D D D D D A
READ DATA
ADDITONAL
SEQUENTIAL READ
DATA BYTES
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
ACKNOWLEDGE GENERATED BY I²C MASTER
READ DATA (LAST BYTE)
D D D D D D D D ~A
STOP
Figure 24. I²C Multiple Register Read Sequence
START
WRITE ADDRESS
BYTE 3: DEVICE ADDRESS
READ DATA
BYTE 4: REG(N)[7:0] DATA
READ DATA
READ DATA (LAST BYTE)
STOP
SDA
1 0 0 1 0 A1 A0 R A D D D D D D D D A
ADDITONAL
D D D D D D D D ~A
SCL
SEQUENTIAL READ
DATA BYTES
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
Figure 25. I²C Streamlined Register Read Sequence
ACKNOWLEDGE GENERATED BY I²C MASTER
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