MAX536 Datasheet, PDF (4/24 Pages) Maxim Integrated Products – Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(V_DD = +15V, V_SS = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, R_L = 5kΩ, C_L = 100pF, T_A = T_MIN to T_MAX, unless
otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS (Note 5)
CONDITIONS
Internal Power-On Reset
Pulse Width (Note 2)
t_POR
SCK Clock Period
SCK Pulse Width High
SCK Pulse Width Low
CS Fall to SCK Rise
Setup Time
SCK Rise to CS Rise
Hold Time
SDI Setup Time
SDI Hold Time
SCK Rise to SDO Valid
Propagation Delay (Note 6)
SCK Fall to SDO Valid
Propagation Delay (Note 7)
CS Fall to SDO Enable
(Note 8)
t_CP
t_CH
t_CL
t_CSS
t_CSH
t_DS
t_DH
t_DO1
t_DO2
t_DV
1kΩ pull-up on SDO
to V_{DD, CLOAD} = _50pF
1kΩ pull-up on SDO
to V_{DD, CLOAD} = _50pF
SDO high
SDO low
SDO high
SDO low
CS Rise to SDO Disable
(Note 9)
t_TR
SCK Rise to CS Fall Delay
CS Rise to SCK Rise
Hold Time
LDAC Pulse Width Low
CS Pulse Width High
t_CS0
t_CS1
t_LDAC
t_CSW
Continuous SCK, SCK edge ignored
SCK edge ignored
MIN TYP MAX UNITS
20
µs
100
ns
30
ns
30
ns
20
ns
10
ns
40
26
ns
0
ns
78
105
ns
50
80
81
110
ns
53
85
27
45
ns
40
60
ns
20
ns
20
ns
30
ns
40
ns
Note 1: TUE is specified with no resistive load.
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I_{DD decreases slightly.}
Note 5: All input signals are specified with t_R = t_F ≤ 5ns. Logic input swing is 0V to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pull-up.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.
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