MAX1684 Datasheet, PDF (4/16 Pages) Maxim Integrated Products – Low-Noise, 14V Input, 1A, PWM Step-Down Converters

Low-Noise, 14V Input, 1A, PWM
Step-Down Converters
ELECTRICAL CHARACTERISTICS
(V_IN = V _SHDN = +6V, STBY = SYNC/PWM = CVL, V_BOOT = V_OUT, FB = AGND, circuit of Figure 1, T_A = -40°C to +85°C, unless other-
wise noted.) (Note 5)
PARAMETER
Input Voltage Range
Output Feedback Voltage
Output Voltage (3.3V mode)
Output Current Capability
Output Adjust Range
FB Input Current
Current Limit in PWM Mode
Current Limit in Low-Power
Mode
SYMBOL
CONDITIONS
V_FB
V_OUT
I_FB
I_LIM
I_LIMLP
V_FB = V_OUT, I_LOAD = 0 to 1A
FB = AGND, I_LOAD = = 0 to 1A
V_IN = 6V to 14V
BOOT = AGND (Note 1)
V_FB = 1.4V
STBY = low
MIN
2.7
1.236
3.295
1
V_REF
-50
1.2
285
MAX
14
1.266
3.375
V_IN
50
2.3
UNITS
V
V
V
A
V
nA
A
475
mA
Quiescent Power Consumption
Shutdown Supply Current
Oscillator Frequency
Reference Output Voltage
CVL Regulator Output Voltage
f_OSC
Normal mode, SYNC/PWM = low,
V_BOOT = 3.3V (Note 2)
Low-power mode, STBY = low,
V_BOOT = 3.3V (Note 2)
SHDN = low
MAX1684
MAX1685
I_REF = 0
V_IN = 3V to 14V, BOOT = AGND,
I_CVL = 0 to 5mA
240
480
1.236
2.7
2
mW
0.27
6
µA
350
kHz
700
1.266
V
3.15
V
CVL Undervoltage Lockout
Threshold
BOOT = AGND, CVL falling edge,
typical hysteresis is 40mV
2.4
2.6
V
CVH with Respect to V_IN
BOOT Switchover Threshold
ILIM/SS Source Current
Logic Input High Voltage
Logic Input Low Voltage
I_CVH = -1mA
-5.0
BOOT falling edge, typical hysteresis is 0.1V
2.4
V_ILIM/SS = 1.4V
3.1
V_IH
SHDN, STBY, SYNC/PWM
2
V_IL
-4.1
V
2.6
V
4.7
µA
V
0.7
Note 1: The output adjust range with BOOT connected to V_OUT is V_REF to 5.5V. Connect BOOT to AGND for V_OUT > 5.5V.
Note 2: The quiescent power-consumption specifications include chip supply and gate-drive loss only. Divide these values by V_IN
(= 6V) to obtain quiescent currents. In normal and low-power modes, chip supply current dominates and quiescent power
is proportional to V_BOOT (BOOT connected to OUT). In PWM mode, gate-drive loss dominates and quiescent power is pro-
portional to V_IN · (V_IN - V_CVH). In addition, IR losses in power switches and external components typically increase PWM
quiescent power consumption by 5mW to 10mW. Note that if the device is not bootstrapped, additional power will be dissi-
pated in the CVL linear regulator.
Note 3: When the duty factor (V_OUT / V_IN) is less than this value, the switching frequency decreases in PWM mode to maintain regu-
lation.
Note 4: Thermal shutdown is disabled in low-power mode (STBY = low) to reduce power consumption.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
4 _______________________________________________________________________________________