MAX1644 Datasheet, PDF (4/32 Pages) Maxim Integrated Products – Advanced Chemistry-Independent, Level 2 Battery Charger with Input Current Limiting

Advanced Chemistry-Independent, Level 2
Battery Charger with Input Current Limiting
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = +3.3V, VBATT = +16.8V, VDCIN = +18V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
DC-TO-DC CONVERTER SPECIFICATIONS
Minimum Off-Time
tOFF
Maximum On-Time
tON
Maximum Duty Cycle
LX Input Bias Current
VDCIN = 28V, VBATT = VLX = 20V
LX Input Quiescent Current
VDCIN = 0, VBATT = VLX = 20V
BST Supply Current
DHI high
DLOV Supply Current
VDLOV = VLDO, DLO low
Inductor Peak Current Limit
RCSI = 50mΩ
DHI Output Resistance
DHI high or low, VBST - VLX = 4.5V
DLO Output Resistance
DLO high or low, VDLOV = 4.5V
THERMISTOR COMPARATOR SPECIFICATIONS
MIN TYP MAX UNITS
1
1.25
1.5
µs
5
10
15
ms
99 99.99
%
200
500
µA
1
µA
6
15
µA
5
10
µA
5.0
6.0
7.0
A
6
14
Ω
6
14
Ω
THM Input Bias Current
VTHM = 4% of VDD to 96% of VDD,
V_DD = 2.8V to 5.65V
-1
1
µA
Thermistor Overrange Threshold
Thermistor Cold Threshold
Thermistor Hot Threshold
VDD = 2.8V to 5.65V, VTHM falling
VDD = 2.8V to 5.65V, VTHM falling
VDD = 2.8V to 5.65V, VTHM falling
89.5
74
22
91
75.5
23.5
92.5
77
25
% of VDD
% of VDD
% of VDD
Thermistor Underrange
Threshold
VDD = 2.8V to 5.65V, VTHM falling
6
7.5
9 % of V_DD
Thermistor Comparator
Threshold Hysteresis
All 4 comparators, VDD = 2.8V to 5.65V
SMB INTERFACE LEVEL SPECIFICATIONS (VDD = 2.8V to 5.65V)
SDA/SCL Input Low Voltage
SDA/SCL Input High Voltage
SDA/SCL Input Hysteresis
SDA/SCL Input Bias Current
SDA Output Low Sink Current
VSDA = 0.4V
INT Output High Leakage
VINT = 5.65V
INT Output Low Voltage
IINT = 1mA
SMB INTERFACE TIMING SPECIFICATIONS (VDD = 2.8V to 5.65V, Figures 4 and 5)
SCL High Period
tHIGH
SCL Low Period
tLOW
Start Condition Setup Time
from SCL
tSU:STA
1
% of VDD
0.6
V
1.4
V
220
mV
-1
1
µA
6
mA
1
µA
25
200
mV
4
µs
4.7
µs
4.7
µs
Start Condition Hold Time
from SCL
SDA Setup Time from SCL
SDA Hold Time from SCL
tHD:STA
tSU:DAT
t_HD:DAT
4
µs
250
ns
0
ns
4 _______________________________________________________________________________________