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MAX1429 Datasheet, PDF (4/18 Pages) Maxim Integrated Products – 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS (DVCC = DRVCC = 3.3V)
CLKP/CLKN Duty Cycle
Duty Cycle
Effective Aperture Delay
tAD
Output Data Delay
Data Valid Delay
tDAT
tDAV
(Note 3)
(Note 3)
Pipeline Latency
tLATENCY
CONDITIONS
MIN TYP MAX UNITS
50 ±5
%
230
ps
2.8
4.1
6.5
ns
5.3
6.3
8.6
ns
3
Clock
cycles
CLKP Rising Edge to DATA Not
Valid
tDNV (Note 3)
2.5
3.4
5.2
ns
CLKP Rising Edge to DATA Valid
(guaranteed)
tDGV (Note 3)
3.2
4.4
7.4
ns
DATA Setup Time (Before DAV
Rising Edge)
tSETUP (Note 3)
tCLKP + tCLKP + tCLKP +
ns
0.2
1.7
2.8
DATA Hold Time (After DAV
Rising Edge)
POWER REQUIREMENTS
tHOLD (Note 3)
tCLKN - tCLKN - tCLKN -
ns
3.5
2.7
2.0
Analog Supply Voltage Range
AVCC
5
±3%
V
Digital-Supply Voltage Range
DVCC (Note 2)
2.3 to
2.5
V
Output-Supply Voltage Range
Analog Supply Current
Digital + Output Supply Current
Total Power Dissipation
DRVCC (Note 2)
IAVCC
IDVCC +
IDRVCC
PDISS
fCLK = 100MHz, CL = 5pF
2.3 to
2.5
V
390 440
mA
38
44
mA
2045
mW
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of fSAMPLE = 100.007936MHz, an
input frequency of fIN = fSAMPLE x (4915/32768) = 15.000580MHz, and a frequency bin size of 3052Hz. Close-in (fIN ±
36.6kHz) and low-frequency (DC to 73.2kHz) bins are excluded from the spectrum analysis.
Note 2: Apply the same voltage levels to DVCC and DRVCC.
Note 3: Guaranteed by design and characterization.
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