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MAX1169_10 Datasheet, PDF (4/20 Pages) Maxim Integrated Products – 58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Input Current
Input Capacitance
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage
AVDD
Digital Supply Voltage
DVDD
Internal reference
(powered down
between conversions,
R/W = 0)
fSAMPLE = 58.6ksps
fSAMPLE = 10ksps
fSAMPLE = 1ksps
Shutdown
fSAMPLE = 58.6ksps
Analog Supply Current
IAVDD
Internal reference
fSAMPLE = 10ksps
(always on, R/W = 1) fSAMPLE = 1ksps
Shutdown
fSAMPLE = 58.6ksps
External reference
(REFADJ = AVDD)
fSAMPLE = 10ksps
fSAMPLE = 1ksps
Shutdown
fSAMPLE = 58.6ksps
Digital Supply Current
IDVDD
fSAMPLE = 10ksps
fSAMPLE = 1ksps
Shutdown
Power-Supply Rejection Ratio
PSRR VAVDD = 5V ±5%, full-scale input (Note 8)
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)
Serial Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
MIN
4.75
2.7
1.3
TYP
15
MAX
±10
UNITS
μA
pf
1.8
0.7
40
0.4
1.8
1.4
1.1
0.4
0.90
0.36
40
0.4
260
65
6
0.2
5
5.25
V
5.5
V
2.5
mA
μA
5
2.5
mA
μA
5
1.8
mA
μA
5
400
μA
5
16 LSB/V
400
kHz
μs
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition (Sr)
tHD, STA
tLOW
tHIGH
tSU, STA
0.6
μs
1.3
μs
0.6
μs
0.6
μs
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
tHD, DAT
tSU, DAT
(Note 9)
tR
(Note 10)
0
100
20 + 0.1CB
900
ns
ns
300
ns
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
tF
tSU, STO
CB
tSP
(Note 10)
20 + 0.1CB
0.6
300
ns
μs
400
pF
50
ns
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