MAX11206 Datasheet, PDF (4/27 Pages) Maxim Integrated Products – 20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO

20-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply
Digital Supply
Total Operating Current
VAVDD
VDVDD
AVDD + DVDD
Buffers disabled
Buffers enabled
2.7
3.6
V
1.7
3.6
V
235
300
FA
255
AVDD Sleep Current
0.15
2
FA
AVDD Operating Current
Buffers disabled
Buffers enabled
185
235
FA
205
DVDD Sleep Current
0.25
2
FA
DVDD Operating Current
50
65
FA
SPI TIMING CHARACTERISTICS
SCLK Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to 1st SCLK Rise Setup
CS High to 17th SCLK Setup
fSCLK
tCP
tCH
tCL
tCSS0
tCSS1
60% duty cycle at 5MHz
5
MHz
200
ns
80
ns
80
ns
40
ns
40
ns
CS High After 16th SCLK
Falling Edge Hold
tCSH1
3
ns
CS Pulse-Width High
DIN to SCLK Setup
DIN Hold After SCLK
tCSW
tDS
tDH
40
ns
40
ns
0
ns
RDY/DOUT Transition Valid After
SCLK Fall
tDOT
Output transition time, data changes on fall-
ing edge of SCLK
40
ns
RDY/DOUT Remains Valid After
SCLK Fall
tDOH
Output hold time allows for negative edge
data read
3
ns
RDY/DOUT Valid Before SCLK Rise tDOL tDOL = tCL - tDOT
40
ns
CS Rise to RDY/DOUT Disable
CS Fall to RDY/DOUT Valid
tDOD CLOAD = 20pF
Default value of RDY is 1 for minimum spec-
tDOE ification; maximum specification for valid 0
0
on RDY/DOUT
25
ns
40
ns
DATA Fetch
Maximum time after RDY asserts to read
tDF DATA register; t_CNV is the time for one
0
conversion
tCNV -
60 x tCP
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full scale.
Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
lower or continuous data rate of 60sps/50sps.
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