MAX11205 Datasheet, PDF (4/14 Pages) Maxim Integrated Products – 16-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface

16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Rising Edge Data Hold
Time
t4
Allows for positive edge data read
3
ns
RDY/DOUT Fall to SCLK Rising
Edge
t5
0
ns
Next Data Update Time;
No Read Allowed
Data Conversion Time
Data Ready Time After
Calibration Starts (CAL + CNV)
SCLK High After RDY/DOUT Goes
Low to Activate Sleep Mode
Time from RDY/DOUT Low to
SCLK High for Sleep Mode
Activation
MAX11205A
t6
MAX11205B
MAX11205A
t7
MAX11205B
MAX11205A
t8
MAX11205B
MAX11205A
t9
MAX11205B
MAX11205A
t10
MAX11205B
155
Fs
169
8.6
ms
73
208.3
ms
256.1
0
8.6
ms
0
73
0
8.6
ms
0
73
Data Ready Time After Wake-Up
from Sleep Mode
MAX11205A
t11
MAX11205B
8.6
ms
73
Data Ready Time After
Calibration from Sleep Mode
Wake-Up (CAL + CNV)
MAX11205A
t12
MAX11205B
208.4
ms
256.2
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: Positive full-scale error includes zero-scale errors.
Note 6: Tested with VREF = 1.8V.
Note 7: The MAX11205A has no normal-mode rejection at 50Hz or 60Hz.
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