MAX1064 Datasheet, PDF (4/20 Pages) Maxim Integrated Products – 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = V_LOGIC = +5V ±10%, COM = GND, REFADJ = V_DD, V_REF = +2.5V, 4.7µF capacitor at REF pin, f_CLK = 7.6MHz (50% duty
cycle), T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
SYMBOL
V_DD
V_LOGIC
CONDITIONS
MIN TYP MAX UNITS
4.5
5.5
V
2.7
V_DD +
0.3
V
Positive Supply Current
V_LOGIC Current
Power-Supply Rejection
I_DD
I_LOGIC
PSR
Operating mode,
f_SAMPLE = 400ksps
Internal reference
External reference
Standby mode
Operating mode,
Internal reference
External reference
Shutdown mode
C_L = 20pF
f_SAMPLE = 400ksps
Nonconverting
V_DD = 5V ±10%, full-scale input
2.9
3.4
2.5
2.9
mA
1.0
1.2
0.5
0.8
2
10
µA
200
µA
2
10
±0.3 ±0.9 mV
TIMING CHARACTERISTICS
(V_DD = V_LOGIC = +5V ±10%, COM = GND, REFADJ = V_DD, V_REF = +2.5V, 4.7µF capacitor at REF pin, f_CLK = 7.6MHz (50% duty
cycle), T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR Setup Time
CLK or WR to CS Hold Time
CS Pulse Width
WR Pulse Width
SYMBOL
t_CP
t_CH
t_CL
t_DS
t_DH
t_CWS
t_CWH
t_CSWS
t_CSWH
t_CS
t_WR
(Note 8)
CONDITIONS
MIN TYP MAX UNITS
132
ns
40
ns
40
ns
40
ns
0
ns
40
ns
40
ns
60
ns
0
ns
100
ns
60
ns
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