DS89C450-K00 Datasheet, PDF (4/12 Pages) Maxim Integrated Products – DS89C450 Evaluation Kit

DS89C450-K00, DS89C450 Evaluation Kit
Serial Ports
Both serial ports of the DS89C450 (Serial Port 0 and Serial Port 1) are translated to RS-232 levels and brought out
to DB9 connectors at J2 and J3. Serial Port 0 (J2) must always be used when communicating with the bootloader.
Memory
The external memory of the DS89C450 on this evaluation kit is designed to operate with the address and data bus
multiplexed on P0 and P2. A 128K x 8 SRAM is installed, which is accessed as both program and data memory by
this multiplexed bus. Note that as the total memory space of the DS89C450 is only 64K of program memory and
64K of data memory, port pin memory banking must be used to access the entire 128K-memory space.
CPLD
The CPLD device on the evaluation kit board is preprogrammed to perform several functions.
· Address latching of the low 8 bits of the external memory address from port P0.
· Mapping together program and data memory.
· Performing port pin memory banking (optional).
The RTL code preprogrammed into the CPLD is as follows.
module Eval(AD, nRD, ALE, nPSEN, CFG0, CFG1, SW_IN, P1, A, A16, A17, nOE, SW_OUT);
input
input
input
input
input
input
input
[7:0] AD;
nRD;
ALE;
nPSEN;
CFG0;
CFG1;
SW_IN;
// Multiplexed low-order address and data from micro
// Data memory read enable from micro
// Address latch enable from micro
// Program memory read enable from micro
// Configuration input zero (from DIP switch)
// Configuration input one (from DIP switch)
// Interrupt switch input (from pushbutton)
inout [7:0] P1;
// Port 1 from micro
output [7:0] A;
// Demultiplexed low-order address to RAM
output
A16; // Address line to RAM
output
A17; // Address line to RAM
output
nOE; // Output enable to RAM
output
SW_OUT; // Interrupt switch output (to micro)
reg [7:0] A;
always @(negedge ALE) begin
A <= AD;
end
assign A16 = (CFG0 == 0) ? P1[0] : 1'b0;
assign A17 = (CFG0 == 0) ? P1[1] : 1'b0;
assign P1[0] = (CFG1 == 0) ? SW_IN : 1'bz;
assign P1[1] = (CFG1 == 0) ? SW_IN : 1'bz;
assign P1[2] = (CFG1 == 0) ? SW_IN : 1'bz;
assign P1[3] = (CFG1 == 0) ? SW_IN : 1'bz;
assign P1[4] = (CFG1 == 0) ? ~SW_IN : 1'bz;
assign P1[5] = (CFG1 == 0) ? ~SW_IN : 1'bz;
assign P1[6] = (CFG1 == 0) ? ~SW_IN : 1'bz;
assign P1[7] = (CFG1 == 0) ? ~SW_IN : 1'bz;
assign nOE = nRD & nPSEN;
assign SW_OUT = SW_IN;
endmodule
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