DS1556_10 Datasheet, PDF (4/18 Pages) Maxim Integrated Products – 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM

Figure 1. Block Diagram
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Maxim
DS1556
Table 1. Operating Modes
V_CC
CE OE WE
V_IH X X
V_CC > V_PF
V_IL X V_IL
V_IL V_IL V_IH
V_IL V_IH V_IH
V_SO < V_CC <V_PF X
X
X
V_CC <V_SO < V_PF X
X
X
DQ0–DQ7
High-Z
D_IN
D_OUT
High-Z
High-Z
High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1556 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t_AA after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (t_CEA) or at output enable access time (t_OEA). The state of the data input/output pins (DQ) is
controlled by CE and OE. If the outputs are activated before t_AA, the data lines are driven to an
intermediate state until t_AA. If the address inputs are changed while CE and OE remain valid, output data
will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
DATA WRITE MODE
The DS1556 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the
cycle. CE and WE must return inactive for a minimum of t_WR prior to the initiation of a subsequent read
or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for t_DH afterward. In
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