DS1236AS-5 Datasheet, PDF (4/19 Pages) Maxim Integrated Products – MicroManager Chip

DS1236
NON-MASKABLE INTERRUPT
The DS1236 generates a non-maskable interrupt NMI for early warning of power failure to a
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (Figure 6) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point V_TP is 2.54 volts, the proper values
for R1 and R2 can be determined by the equation as shown in Figure 6. Proper operation of the DS1236
requires that the voltage at the IN pin be limited to V_IN. Therefore, the maximum allowable voltage at the
supply being monitored (V_MAX) can also be derived as shown in Figure 6. A simple approach to solving
this equation is to select a value for R2 high enough to keep power consumption low, and solve for R1.
The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power
supply system, maximizing the amount of time for microprocessor shutdown between NMI and RST or
RST .
When the supply being monitored decays to the voltage sense point, the DS1236 pulses the NMI output
to the active state for a minimum of 200 μs. The NMI power-fail detection circuitry also has built-in time
domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33 μs/cycle). Three consecutive samplings of
out-of-tolerance supply (below V_SENSE) must occur at the IN pin to activate NMI . Therefore, the supply
must be below the voltage sense point for approximately 100 μs or the comparator will reset. In this way,
power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any IN pin levels below V_TP are disabled from reaching the NMI pin until V_CC rises to V_CCTP. As a result,
any potential NMI pulse will not be initiated until V_CC reaches V_CCTP.
Removal of an active low level on the NMI pin is controlled by either an internal time-out (when IN pin
is less than V_TP) or by the subsequent rise of the IN pin above V_TP. The initiation and removal of the NMI
signal during power-up results in an NMI pulse of from 0 μs minimum to 500 μs maximum, depending
on the relative voltage relationship between V_CC and the IN pin voltage. As an example, when the IN pin
is tied to ground during power-up, the internal time-out will result in a pulse of 200 μs minimum to 500
μs maximum. In contrast, if the IN pin is tied to V_CCO during power-up, NMI will not produce a pulse on
power-up. Note that a fast slewing power supply may cause the NMI to be virtually nonexistent on
power-up. This is of no consequence, however, since an RST will be active.
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