MAX16031_10 Datasheet, PDF (38/41 Pages) Maxim Integrated Products – EEPROM-Based System Monitors with Nonvolatile Fault Memory

EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the ris-
ing edge of TCK, the controller enters the update-IR state.
Pause-IR: Shifting of the instruction shift register is halt-
ed temporarily. With TMS high, a rising edge on TCK
puts the controller in the exit2-IR state. The controller
remains in the pause-IR state if TMS is low during a ris-
ing edge on TCK.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of
TCK in this state.
Update-IR: The instruction code that has been shifted
into the instruction shift register is latched to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the
run-test/idle state. With TMS high, the controller enters
the select-DR-scan state.
Instruction Register
The instruction register contains a shift register as well
as a latched parallel output and is 5 bits in length.
When the TAP controller enters the shift-IR state, the
instruction shift register is connected between TDI and
TDO. While in the shift-IR state, a rising edge on TCK with
TMS low shifts the data one stage toward the serial output
at TDO. A rising edge on TCK in the exit1-IR state or the
exit2-IR state with TMS high moves the controller to the
update-IR state. The falling edge of that same TCK latch-
es the data in the instruction shift register to the instruc-
tion register parallel output. Instructions supported by the
MAX16031/MAX16032 and their respective operational
binary codes are shown in Table 16.
SAMPLE/PRELOAD: This is a mandatory instruction
for the IEEE 1149.1 specification that supports two
functions. The digital I/Os of the device are sampled at
the boundary scan test data register without interfering
with the normal operation of the device by using the
capture-DR state. SAMPLE/PRELOAD also allows the
device to shift data into the boundary scan test data
register through TDI using the shift-DR state.
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through
the 1-bit bypass test data register. This allows data to
pass from DTDI to TDO without affecting the device’s
normal operation.
EXTEST: This instruction allows testing of all intercon-
nections to the device. When the EXTEST instruction is
latched in the instruction register, the following actions
occur. Once enabled through the update-IR state, the
parallel outputs of all digital outputs are driven. The
boundary scan test data register is connected between
TDI and TDO. The capture-DR samples all digital inputs
into the boundary scan test data register.
IDCODE: When the IDCODE instruction is latched into
the parallel instruction register, the identification test
data register is selected. The device identification code
is loaded into the identification test data register on the
rising edge of TCK following entry into the capture-DR
state. Shift-DR is used to shift the identification code
out serially through TDO. During test-logic-reset, the
identification code is forced into the instruction register.
The ID code always has a 1 in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number
and number of continuation bytes followed by 16 bits
for the device and 4 bits for the version. See Table 17.
Table 16. JTAG Instruction Set
INSTRUCTION
BYPASS
IDCODE
SAMPLE/PRELOAD
EXTEST
USERCODE
LOAD ADDRESS
READ DATA
WRITE DATA
REBOOT
SAVE
BINARY CODE
11111
00000
00001
00010
00100
01000
01001
01010
01100
01101
SELECTED REGISTER/ACTION
Bypass
Identification
Boundary scan
Boundary scan
User-code data
Memory address
Memory read
Memory write
Resets the device
Stores current fault information in EEPROM
38 ______________________________________________________________________________________