MAX1816 Datasheet, PDF (35/49 Pages) Maxim Integrated Products – Dual Step-Down Controllers Plus Linear- Regulator Controller for Notebook Computers

Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
UNDEFINED
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
0
0.5 0.8 1.0 1.2 1.5
2.0
OFS_ INPUT VOLTAGE (V)
Figure 9. Offset-Control Transfer Function
REF OR V_OUT1
REF OR V_OUT1
OFS0
OFS0
OFS1 OR
OFS1
OFS1
OFS2
Figure 10. Simplified Offset-Control Circuits
At the beginning of an output voltage transition, the regu-
lator is placed in forced-PWM mode and the PGOOD
output is high. If there is a fault on BUCK2 during this
period, PGOOD goes low. The output voltage follows the
internal DAC code, which changes in 25mV increments
until it reaches the programmed VID code. The regulator
remains in forced-PWM mode for 32 clock cycles after
the transition to ensure that the output settles properly.
The PGOOD output is forced high for 4 clock cycles after
the transition also to allow the output to settle. The slew-
rate clock frequency (set by the R_TIME resistor) must be
set fast enough to ensure that the longest transition is
completed within the allotted time interval.
The output voltage transition is performed in 25mV steps,
preceded by a 4µs delay and followed by one additional
clock period. The total time for a transition depends on
R_TIME, the voltage difference, and the accuracy of the
MAX1816/MAX1994s’ slew-rate clock, and is not depen-
dent on the total output capacitance. The greater the out-
put capacitance, the higher the surge current required
for the transition. The MAX1816/MAX1994 automatically
control the current to the minimum level required to com-
plete the transition in the calculated time. As long as the
surge current is less than the current limit set by ILIM1,
the transition time is given by:
t_SLEW
≤
4µs
+



1
f_SLEW
₁₊
V_OLD − V_NEW
25mV




where f_SLEW = 252kHz × 143kΩ / R_TIME, V_OLD is the
original DAC setting, and V_NEW is the new DAC setting.
See Time Frequency Accuracy in the Electrical
Characteristics table for f_SLEW accuracy. The practical
range of R_TIME is 68kΩ to 680kΩ, corresponding to
1.9µs to 19µs per 25mV step. Although the DAC takes
discrete 25mV steps, the output filter makes the transi-
tions relatively smooth. The average inductor current
required to make an output voltage transition is:
I_L ≅ C_OUT ✕ _25mV ✕ f_SLEW
The slew-rate controller also performs a soft-start and
soft-stop function. The soft-start function works by
counting up from zero, in order to minimize turn-on
surge currents. The soft-stop executes this process in
reverse, eliminating the negative output voltages and
the need for an external Schottky output clamp diode
that would otherwise be required if DL1 were simply
forced high.
Setting BUCK2 Output Voltage
BUCK2’s Dual Mode^™ operation allows the selection of
common voltages without requiring external compo-
nents (Figure 1). In fixed mode, connect FB2 to AGND
for 2.5V output, or connect FB2 to V_CC for 1.8V output.
In adjustable mode, the output voltage can be adjusted
from 1.0V to 5.5V using a resistive voltage-divider from
the BUCK2 output to AGND with the center tap con-
nected to FB2 (Figure 11). The equation for adjusting
the output voltage is:
V_OUT2
=

V_{FB2 }1+

R1^
R2


where V_FB2 is 1.0V.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
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