MAX9272A_14 Datasheet, PDF (32/47 Pages) –

MAX9272A
28-Bit GMSL Deserializer for Coax or STP Cable
Additional Error Detection and Correction
In default mode (additional error detection and correc-
tion disabled), data encoding/decoding is the same as in
previous GMSL serializers/deserializers (parity only). At
the serializer, the parallel input word is scrambled and a
parity bit is added. The scrambled word is divided into 3 or
4 bytes (depending on the BWS setting), 8b/10b encoded,
and then transmitted serially. At the deserializer, the same
operations are performed in reverse order. The parity bit
is used by the deserializer to find the word boundary and
for error detection. Errors are counted in an error counter
register and an error pin indicates errors.
The deserializer can use one of two additional error-
detection/correction methods (selectable by register set-
ting):
1) 6-bit cyclic redundancy check
2) 6-bit hamming code with 16-word interleaving
Cyclic Redundancy Check (CRC)
When CRC is enabled, the serializer adds 6 bits of CRC
to the input data. This reduces the available bits in the
input data word by 6, compared to the non-CRC case
(see Table 2 for details). For example, 16 bits are avail-
able for input data instead of 22 bits when BWS = 0, and
24 bits instead of 30 bits when BWS = 1.
The CRC generator polynomial is x⁶ + x + 1 (as used in
the ITU-T G704 telecommunication standard).
The parity bit is still added when CRC is enabled,
because it is used for word-boundary detection. When
CRC is enabled, each data word is scrambled and then
the 6-bit CRC and 1-bit parity are added before the 8b/10b
encoding.
At the deserializer, the CRC code is recalculated. If the
recalculated CRC code does not match the received CRC
code, an error is flagged. This CRC error is reported to the
error counter.
Hamming Code
Hamming code is a simple and effective error-correction
code to detect and/or correct errors. The MAX9272A
deserializer (when used with the MAX9271/MAX9273
GMSL serializers) uses a single-error correction/double-
error detection per pixel hamming-code scheme.
The deserializer uses data interleaving for burst error tol-
erance. Burst errors up to 11 consecutive bits on the serial
link are corrected and burst errors up to 31 consecutive
bits are detected.
Hamming code adds overhead similar to CRC. See Table 2
for details regarding the available input word size.
HS/VS Encoding and/or Tracking
HS/VS encoding by a GMSL serializer allows horizontal
and vertical synchronization signals to be transmitted
while conserving pixel data bandwidth. With HS/VS encod-
ing enabled, 10-bit pixel data with a clock up to 100MHz
can be transmitted using one video pixel of data per HS/
VS transition versus 8-bit data with a clock up to 100MHz
without HS/VS encoding. The deserializer performs HS/
VS decoding, tracks the period of the HS/VS signals, and
uses voting to filter HS/VS bit errors. When using HS/VS
encoding, use a minimum HS/VS low-pulse duration of
two PCLKOUT cycles when DBL = 0 on the deserializer.
When DBL = 1, use a minimum HS/VS low-pulse duration
of five PCLKOUT cycles and a minimum high-pulse dura-
tion of two PCLKOUT cycles. When using hamming code
with HS/VS encoding, do not send more than two transi-
tions every 16 PCLKOUT cycles.
When the serializer uses double-input mode (DBL = 1),
the active duration, plus the blanking duration of HS or VS
signals, should be an even number of PCLKOUT cycles.
When DBL = 1 in the serializer and DBL = 0 in the deserial-
izer, two pixel clock cycles of HS/VS at the serializer input
are output at the HS0/VS0 and HS1/VS1 output of the
deserializer in one cycle. The first cycle of HS/VS goes out
of HS0/VS0 and the second cycle goes out of HS1/VS1.
HS1 and VS1 are not used when HVEN = 0.
If HS/VS tracking is used without HS/VS encoding, use
DOUT0 for HSYNC and DOUT1 for VSYNC. In this case,
if DBL values on the serializer/deserializer are different,
set the UNEQDBL register bit in the deserializer to 1. If the
serializer and deserializer have unequal DBL settings and
HVEN = 0, then HS/VS inversion should only be used on
the side that has DBL = 1. HS/VS encoding sends pack-
ets when HSYNC or VSYNC is low; use HS/VS inversion
register bits if input HSYNC and VSYNC signals use an
active-low convention in order to send data packets during
the inactive pixel clock periods.
Serial Input
The device can receive serial data from two kinds of
cables: 100Ω twisted pair and 50Ω coax (contact the
factory for devices compatible with 75I cables).
Coax-Mode Splitter
In coax mode, OUT+ and OUT- of the serializer are active.
This enables use as a 1:2 splitter (Figure 29). In coax
mode, connect OUT+ to IN+ of the deserializer. Connect
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