MAX8662 Datasheet, PDF (32/36 Pages) Maxim Integrated Products – Power-Management ICs for Single-Cell, Li+ Battery-Operated Devices

Power-Management ICs for
Single-Cell, Li+ Battery-Operated Devices
Table 5. MAX8662/MAX8663 Package Thermal Characteristics
48-PIN THIN QFN (6mm x 6mm)
SINGLE-LAYER PCB
MULTILAYER PCB
40-PIN THIN QFN (5mm x 5mm)
SINGLE-LAYER PCB
MULTILAYER PCB
CONTINUOUS
POWER
DISSIPATION
2105.3mW
Derate 26.3mW/°C above
+70°C
2963.0mW
Derate 37.0mW/°C above
+70°C
1777.8mW
Derate 22.2mW/°C above
+70°C
2857.1mW
Derate 35.7mW/°C above
+70°C
θ_JA
38°C/W
θ_JC
1.4°C/W
27°C/W
1.4°C/W
45°C/W
1.7°C/W
28°C/W
1.7°C/W
Power Dissipation
The MAX8662/MAX8663 have a thermal-limiting circuitry,
as well as a shutdown feature to protect the IC from
damage when the die temperature rises. To allow the
maximum charging current and load current on each
regulator, and to prevent thermal overload, it is important
to ensure that the heat generated by the
MAX8662/MAX8663 is dissipated into the PCB. The
package’s exposed paddle must be soldered to the
PCB, with multiple vias tightly packed under the exposed
paddle to ensure optimum thermal contact to the ground
plane.
Table 5 shows the thermal characteristics of the
MAX8662/MAX8663 packages. For example, the junc-
tion-to-case thermal resistance (θ_JC) of the MAX8663 is
2.7°C/W. When properly mounted on a multilayer PCB,
the junction-to-ambient thermal resistance (θ_JA) is typi-
cally 28°C/W.
PCB Layout and Routing
High switching frequencies and relatively large peak
currents make the PCB layout a very important aspect of
design. Good design minimizes ground bounce, exces-
sive EMI on the feedback paths, and voltage gradients
in the ground plane, which can result in instability or
regulation errors.
A separate low-noise analog ground plane containing
the reference, linear regulator, signal ground, and GND
must connect to the power-ground plane at only one
point to minimize the effects of power-ground currents.
PGND_, DC power, and battery grounds must connect
directly to the power-ground plane. Connect GND to
the exposed paddle directly under the IC. Use multiple
tightly spaced vias to the ground plane under the
exposed paddle to help cool the IC.
Position input capacitors from DC, SYS, BAT, PV1, and
PV2 to the power-ground plane as close as possible to
the IC. Connect input capacitors and output capacitors
from inputs of linear regulators to low-noise analog
ground as close as possible to the IC. Connect the
inductors, output capacitors, and feedback resistors as
close to the IC as possible and keep the traces short,
direct, and wide.
Refer to the MAX8662/MAX8663 evaluation kit for a
suitable PCB layout example.
Pin Configurations (continued)
TOP VIEW
30 29 28 27 26 25 24 23 22 21
EN6 31
20 PWM
EN7 32
19 EN5
OUT6 33
18 EN4
IN67 34
17 OUT5
OUT7 35
VL 36
MAX8663
16 IN45
15 OUT4
SL1 37
14 GND
SL2 38
13 CT
PSET 39
12 ISET
POK 40
11 THM
1 2 3 4 5 6 7 8 9 10
THIN QFN
(5mm x 5mm)
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