MAX8660 Datasheet, PDF (32/42 Pages) Maxim Integrated Products – High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications

High-Efficiency, Low-I_Q, PMICs with Dynamic
Voltage Management for Mobile Applications
The Intel XScale processor contains a power manage-
ment unit general configuration register (PCFR). The
default values of this register are compliant with the
MAX8660/MAX8661. However, wake-up performance
can be optimized using this register:
• The PCFR register contains timers for the SYS_DEL
and PWR_DEL timing parameters as shown in Figure
6. Each timer defaults to 125ms. When using the
MAX8660/MAX8661, these timers may be shortened to
2ms to speed up the overall system wake-up delay.
• Enabling the “shorten wake-up delay” function
(SWDD bit) bypasses the SYS_DEL and PWR_DEL
timers and uses voltage detectors on the Intel
XScale processor to optimize the overall system
wake-up delay.
Voltage Monitors, Reset,
and Undervoltage-Lockout Functions
Undervoltage and Overvoltage Lockout
When the V_IN is below V_UVLO (typically 2.35V), the
MAX8660/MAX8661 enter its undervoltage-lockout
mode (UVLO). UVLO forces the device to a dormant
state. In UVLO, the input current is very low (1.5µA)
and all regulators are off. RSO and LBO are forced low
when the input voltage is between 1V (typ) and V_UVLO.
The I²C does not function in UVLO, and the I²C register
contents are reset in UVLO.
When the input voltage is above V_OVLO (typically
6.35V) the MAX8660/MAX8661 enter overvoltage-lock-
out mode (OVLO). OVLO mode protects the MAX8660/
MAX8661 from high-voltage stress. In OVLO, the input
current is 25µA and all regulators are off. RSO is held
low, the I²C does not function, and register contents
are reset in OVLO. LBO continues to function in OVLO;
however, since LBO is typically pulled up to V8
(VCC_BBATT), LBO appears to go low in OVLO
because V8 is disabled. Alternatively, LBO may be
pulled up to IN.
Reset Output (RSO) and MR Input
RSO is an open-drain reset output. As shown in Figure
1, RSO typically connects to the nRESET input of the
Intel XScale processor and is pulled up to V8
(VCC_BBATT). A low on nRESET causes the processor
to enter its reset state.
RSO is forced low when one or more of the following
conditions occur:
• MR is low.
• V8 is below V_RSOTH (2.2V falling typ).
• V_IN is below V_UVLO (2.35V typ).
• V_IN is above V_OVLO (6.35V typ).
RSO is high impedance when all of the following condi-
tions are satisfied:
• MR is high.
• V8 is above V_RSOTH (2.35V rising typ).
• V_UVLO < V_IN < V_OVLO.
• The RSO deassert delay (t_VBHRSTH = 24ms typ) has
expired.
When RSO goes low, the MAX8660/MAX8661 I²C regis-
ters are reset to their default values.
If the MR feature is not required, connect MR high. If
the RSO feature is not required, connect RSO low.
Low-Battery Detector (LBO, LBF, LBR)
LBO is an open-drain output that typically connects to the
nBATT_FAULT input of the Intel XScale processor to indi-
cate that the battery has been removed or discharged
(Figure 1). LBO is typically pulled up to V8 (VCC_BBATT).
LBR and LBF monitor the input voltage (usually a bat-
tery) and trigger the LBO output (Figure 7). The truth
table in Figure 7 shows that LBO is high impedance
when the voltage from LBR to AGND (V_LBR) exceeds
the low-battery rising threshold (V_LBRTH = 1.25V (typ).
LBO is low when the voltage from LBF to AGND (V_LBF)
falls below the low-battery falling threshold (V_LBFTH =
1.20V typ). On power-up, the LBR threshold must be
exceeded before LBO deasserts.
+
IN
R1
LBF
MAX8660
MAX8661
SQ
R2
V_LBFTH
1.200V
LBR
R
R3
V_LBRTH
1.250V
V8
(VCC_BBATT)
LBO
AGND
LBF
V_LBF < V_LBFTH
V_LBF < V_LBFTH
V_LBF > V_LBFTH
V_LBF > V_LBFTH
TRUTH TABLE
LBR
V_LBR < V_LBRTH
V_LBR > V_LBRTH
V_LBR < V_LBRTH
V_LBR > V_LBRTH
LBO
0
0
HOLD
1
Figure 7. Low-Battery Detector Functional Diagram
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