MAX17030 Datasheet, PDF (32/38 Pages) Maxim Integrated Products – 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers

1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
during a downward VID transition in skip mode. During
pulse-skipping operation (DPRSLPVR = high), the OVP
threshold tracks the VID DAC voltage as soon as the
output is in regulation; otherwise, the fixed 1.5V (typ)
threshold is used.
When the OVP circuit detects an overvoltage fault while
in multiphase mode (DPRSLPVR = low, PSI = high), the
MAX17030/MAX17036 immediately force DL1 and DL2
high, PWM3 low, and DRSKP high; and pull DH1 and
DH2 low. This action turns on the synchronous-rectifier
MOSFETs with 100% duty and, in turn, rapidly dis-
charges the output filter capacitor and forces the output
low. If the condition that caused the overvoltage (such
as a shorted high-side MOSFET) persists, the battery
fuse blows. Toggle SHDN or cycle the V_CC power supply
below 0.5V to clear the fault latch and reactivate the con-
troller.
When an overvoltage fault occurs while in 1-phase
operation (DPRSLPVR = high, or PSI = low), the
MAX17030/MAX17036 immediately force DL1 high and
pull DH1 low. DL2 and DH2 remain low as phase 2 was
disabled. DL2 does not react.
Overvoltage protection can be disabled through the no-
fault test mode (see the No-Fault Test Mode section).
Output Undervoltage Protection
If the MAX17030/MAX17036 output voltage is 400mV
below the target voltage, the controller activates the
shutdown sequence and sets the fault latch. Once the
output voltage ramps down to 12.5mV, it forces the DL1
and DL2 low and pulls DH1 and DH2 low, three-states
PWM3, and sets DRSKP low 10Ω CSNI discharge FET
is turned on. Toggle SHDN or cycle the V_CC power
supply below 0.5V to clear the fault latch and reactivate
the controller.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
Thermal-Fault Protection
The MAX17030/MAX17036 feature a thermal fault-pro-
tection circuit. When the junction temperature rises
above +160°C, a thermal sensor sets the fault latch and
forces the DL1 and DL2 low and pulls DH1 and DH2
low, three-states PWM3, sets DRSKP low, and enables
10Ω CSNI discharge FET on. Toggle SHDN or cycle the
V_CC power supply below 0.5V to clear the fault latch
and reactivate the controller after the junction tempera-
ture cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched fault-protection features can complicate
the process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to deter-
mine what went wrong. Therefore, a “no-fault” test
mode is provided to disable the fault protection—over-
voltage protection, undervoltage protection, and ther-
mal shutdown. Additionally, the test mode clears the
fault latch if it has been set. The no-fault test mode is
entered by forcing 11V to 13V on SHDN.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moder-
ate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V_IN -
V_OUT differential exists. The high-side gate drivers (DH)
source 2.7A and sink 2.2A, and the low-side gate dri-
vers (DL) source 2.7A and sink 8A. This ensures robust
gate drive for high-current applications. The DH_ float-
ing high-side MOSFET drivers are powered by internal
boost switch charge pumps at BST_, while the DL_ syn-
chronous-rectifier drivers are powered directly by the
5V bias supply (V_DD).
Adaptive dead-time circuits monitor the DL and DH dri-
vers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
A low-resistance, low-inductance path from the DL and
DH drivers to the MOSFET gates is required for the
adaptive dead-time circuits to work properly; otherwise,
the sense circuitry in the MAX17030/MAX17036 inter-
prets the MOSFET gates as “off” while charge actually
remains. Use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the driver).
The DL low on-resistance of 0.25Ω (typ) helps prevent
DL from being pulled up due to capacitive coupling from
the drain to the gate of the low-side MOSFETs when the
inductor node (LX) quickly switches from ground to V_IN.
The capacitive coupling between LX and DL created by
the MOSFET’s gate-to-drain capacitance (C_RSS), gate-
to-source capacitance (C_ISS - C_RSS), and additional
board parasitics should not exceed the following mini-
mum threshold to prevent shoot-through currents:
V_GS(TH)
>
V_IN(MAX)
⎛
⎝⎜
C_RSS
C_ISS
⎞
⎠⎟
Adding a 4700pF between DL and power ground (C_NL
in Figure 10), close to the low-side MOSFETs, greatly
reduces coupling. Do not exceed 22nF of total gate
capacitance to prevent excessive turn-off delays.
32 ______________________________________________________________________________________