DS26900_11 Datasheet, PDF (32/49 Pages) Maxim Integrated Products – JTAG Multiplexer/Switch

__________________________________________________________________________________________ DS26900
Register Name:
Register Description:
DCR
6-Bit Device Configuration Register
Bit #
7
Name
—
Reset
—
6
5
4
3
2
1
0
—
TM_SLAVE DPDV
TMSi
TDIi
TDOi
TCKi
—
0
0
0
0
0
0
Bit 5: Test Master Slave Enable (TM_SLAVE). Determines in conjunction with M[1:0] if the DS26900 device will
drive nonmaster TM1/TM2 as slaves. If the TM buses are in parallel with more than one DS26900, only one
DS26900 can drive TM1/TM2 as a slave. The following table describes the combinations.
MODE
Single-Package
Single-Package
Cascade Master
Cascade Extension
Deselect
M[1:0]
00
00
01
10
11
TM_SLAVE BIT
0
1
N/A
N/A
N/A
TM1/TM2 SLAVE CAPABLE
No
Yes
Yes
No
N/A
Bit 4: Deselected Port Drive Values (DPDV). This bit determines the logic levels driving a deselected secondary
port according to the following table. Note: This configuration bit does not apply to TM1 or TM2 in slave mode. TM1
or TM2 port signals in slave mode will never be high impedance.
A secondary port is not selected (deselected) when device is in switch configuration mode, or when the particular
port address is not loaded in the Secondary Port Selection Register (SPSR). The state of this bit can be monitored
via the DPDV pin.
SIGNAL
STMSn
DPDV = 0
0
DPDV = 1
HiZ^*
STRSTn
1
1
STDIn
0
HiZ^*
STCKn
0
0
*HiZ is a high-impedance state with no internal pullup/down resistors active.
Bit 3: Test Mode Select Invert (TMSi). Invert the TMS signal from the arbitrated master to the selected slave port
by setting this bit to logic 1.
Bit 2: Test Data In Invert (TDIi). Invert the TDI signal from the arbitrated master to the selected slave port by
setting this bit to logic 1.
Bit 1: Test Data Out Invert (TDOi). Invert the TDO signal from the selected slave port to the arbitrated master by
setting this bit to logic 1.
Bit 0: Test Clock Invert (TCKi). Invert the TCK from the arbitrated master to the selected slave port by setting this
bit to logic 1.
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