VT1697SB Datasheet, PDF (3/13 Pages) Maxim Integrated Products – Increased Power Density with Fewer External Components

VT1697SB
Electrical Characteristics
V_DD = V_CC = 1.71V - 1.98V, V_DDH = 12V. The  symbol denotes specifications which apply over the following temperature
range: T_J = 0 to 125°C, otherwise specifications are for T_J = 25°C. The # symbol denotes specifications which apply over the
following temperature range: T_J = -25 to 125°C.
Symbol
Parameter
Conditions
Min Typ Max Units
Supply Voltages , Supply Current
V_DD, V_CC
V_DDH
Bias Supply Voltage
Power Train Input Voltage
Shutdown (See Note 1)
1.71
1.98
V
8.5
12.0
14.0
V
0.5
2
µA
Inactive, No Switching (See Note 2)
3.2
5.0
mA
I_CC + I_DD
1.8V Bias Supply Current
I_DDH
12V Bias Supply Current
I_RECON Specification
Load = 0A, V_OUT = 1.8V, Fsw = 1.5MHz
Load = 0A, V_OUT = 1.8V, Fsw = 300KHz
Load = 0A, V_OUT = 1.8V, Fsw = 600KHz
Shutdown (See Note 1)
Inactive, No Switching (See Note 2)
43
61
mA
14
20
mA
29
41
mA
1.3
10
µA
6.5
20
µA
A_I
Current gain (I_L to I_SENSE)
-70A < I_L < 70A
95000
100000 105000
A/A
Temperature Sensor Specifications
T_RANGE
A_TEMP
Temperature Sensor Dynamic Range
Temperature Sensor Gain
–
Temperature Sensor Voltage
Protection Features
T_J = 0°C
0
150
°C
3.01
mV/°C
832
mV
V_{DD_UVLO}
V_{DDH_OVLO}
V_{DDH_UVLO}
V_{BST_UVLO}
V_DD UVLO Threshold (Rising)
V_DD UVLO Threshold (Falling)
V_DDH OVLO Threshold (Rising)
V_DDH OVLO Threshold (Falling)
V_DDH UVLO Threshold (Rising)
V_DDH UVLO Threshold (Falling)
V_BST UVLO Threshold (Rising)
V_BST UVLO Threshold (Falling)
Note 3
Note 3
1.47
1.57
1.64
V
1.41
1.5
1.58
V
15.48
16
16.41
V
14.95
15.5
15.81
V
4.05
4.27
4.40
V
3.90
4.09
4.25
V
1.39
1.52
1.66
V
1.32
1.45
1.57
V
Peak Positive OCP Clamp Level
59
67
80
A
Peak Positive OCP Clamp Delay
63
ns
OCP
Peak Positive OCP Shutdown Level
Peak Positive OCP Shutdown Delay
99
110
121
A
42
ns
OTP
Peak Negative OCP Clamp Level
Peak Negative OCP Delay
Overtemperature Shutdown
Rising Threshold
-79.1
-71.9
-64.7
A
110
ns
140
150
165
°C
PWM Input
V_IH
Input Voltage, High State
V_IL
Input Voltage, Low State
–
Tristate Control Threshold (V_IN Rising)
TS_FAULTB Input
V_DD - 0.20
V
0.20
V
0.63
V
V_IH
TS_FAULTB Digital Threshold V_IH
V_IL
TS_FAULTB Digital Threshold V_IL
0.41
V
0.17
V
Note 1:
Note 2:
Note 3:
T_SENSE, PWM and I_SENSE pins of the slave are pulled LOW by the master. The slave is in this state before master OE is enabled.
Inactive, no switching: PWM signal is tristated by the master. The slave is in this mode when the master sheds a phase (temporarily disabling this slave) to save
power at lighter loads.
V_{BST_UVLO} is measured with respect to VX and not from ground.
3
Maxim Integrated Products, Inc.