MAX961 Datasheet, PDF (3/12 Pages) Maxim Integrated Products – Single/Dual/Quad, Ultra-High-Speed, +3V/+5V,Beyond-the-Rails Comparators

Single/Dual/Quad, Ultra-High-Speed, +3V/+5V,
Beyond-the-Rails Comparators
ELECTRICAL CHARACTERISTICS (continued)
(V_CC = +2.7V to +5.5V, V_CM = 0V, C_OUT = 5pF, V_SHDN = 0V, V_LE = 0V, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
T_A = +25°C
MIN TYP MAX
T_MIN to T_MAX
MIN MAX
Output Capacitance
4
MAX961/MAX963, V_CC = 5V
7.2
11
11
Supply Current
per Comparator
I_CC
MAX962/MAX964, V_CC = 5V
5
8
9
MAX997/MAX999, V_CC = 5V
5
6.5
6.5
Shutdown Supply Current
per Comparator
I_SHDN
MAX961/MAX963/MAX964/
MAX997, V_CC = 5V
0.27
0.5
0.5
UNITS
pF
mA
mA
Shutdown Output
Leakage Current
Rise/Fall Time
Logic Input High
MAX961/MAX963/MAX964/
MAX997, V_OUT = 0.5V and
V_CC - 0.5V
1
20
µA
t_R, t_F V_CC = 5V
2.3
ns
V_IH
(V_CC / 2)
+ 0.4
(V_CC / 2)
+ 0.4
V
Logic Input Low
V_IL
(V_CC / 2)
- 0.4
(V_CC / 2)
- 0.4
V
Logic Input Current
Propagation Delay
Differential Propagation
Delay
I_IL, I_IH
t_PD
t_PD
V_LOGIC = 0V or V_CC
5mV overdrive (Note 7)
Between any two channels or
outputs (Q/Q)
±15
4.5
7
0.3
±30
µA
8.5
ns
ns
Propagation-Delay Skew
Data-to-Latch Setup Time
Latch-to-Data Hold Time
Latch Pulse Width
Latch Propagation Delay
Shutdown Time
t_SKEW
t_SU
t_H
t_LPW
t_LPD
t_OFF
Between t_PD- and t_PD+
MAX961/MAX963 (Note 8)
MAX961/MAX963 (Note 8)
MAX961/MAX963 (Note 8)
MAX961/MAX963 (Note 8)
Delay until output is high-Z
(>10kΩ)
0.3
5
5
5
10
150
ns
5
ns
5
ns
5
ns
10
ns
ns
Shutdown Disable Time
t_ON Delay until output is valid
250
ns
Note 1: The MAX961EUA/MAX962EUA/MAX997EUA/MAX999EUK are 100% production tested at T_A = +25°C; all temperature specifica-
tions are guaranteed by design.
Note 2: Inferred by CMRR. Either input can be driven to the absolute maximum limit without false output inversion, provided that the other
input is within the input voltage range.
Note 3: The input-referred trip points are the extremities of the differential input voltage required to make the comparator output change
state. The difference between the upper and lower trip points is equal to the width of the input-referred hysteresis zone. (See
Figure 1.)
Note 4: Input offset voltage is defined as the mean of the trip points.
Note 5: CMRR = (V_OSL - V_OSH) / 5.2V, where V_OSL is the offset at V_CM = -0.1V and V_OSH is the offset at V_CM = 5.1V.
Note 6: PSRR = (V_OS2.7 - V_OS5.5) / 2.8V, where V_OS2.7 is the offset voltage at V_CC = 2.7V, and V_OS5.5 is the offset voltage at
V_CC = 5.5V.
Note 7: Propagation delay for these high-speed comparators is guaranteed by design characterization because it cannot be accurately
measured using automatic test equipment. A statistically significant sample of devices is characterized with a 200mV step and
100mV overdrive over the full temperature range. Propagation delay can be guaranteed by this characterization, since DC tests
ensure that all internal bias conditions are correct. For low overdrive conditions, V_TRIP is added to the overdrive.
Note 8: Guaranteed by design.
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