MAX9492 Datasheet, PDF (3/11 Pages) Maxim Integrated Products – Multiple-Output Clock Generator with Spread Spectrum

Multiple-Output Clock Generator
with Spread Spectrum
AC ELECTRICAL CHARACTERISTICS
(V_DD = V_DDA = +3.0V to +3.6V, C_L = 10pF, unless otherwise noted. Typical values at V_DD = V_DDA = +3.3V, T_A = +25°C, with CLK1 at
25MHz and all other CLK_ outputs at 133MHz.) (Note 2)
PARAMETER
OUTPUTS (CLK_)
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Crystal Frequency
10
35
MHz
Input Frequency Range
External clock
15
35
MHz
Crystal Frequency Tolerance
∆f_A
-50
+50
ppm
Output-to-Output Skew
Rise Time
Fall Time
Duty Cycle
Output Period Jitter
Power-Up Time
Frequency Spread
t_SKO
t_R1
t_F1
Any two CLK_ outputs
20% V_DD to 80% V_DD
80% V_DD to 20% V_DD
220
ps
1.9
2.5
ns
1.3
2.5
ns
40
60
%
J_P
RMS (SSC = 0), CLK1 is disabled to high
impedance
10
15
ps
t_PO
V_DD > 2.8V to PLL lock
SSC = high
SSC = floating
2
ms
-2.5
%
-1.25
SERIAL INTERFACE TIMING
(V_DD = V_DDA = +3.3V, T_A = -40°C to +85°C.) (Note 1, Figure 1)
PARAMETER
Serial Clock
Bus Free Time Between STOP
and START Conditions
SYMBOL
f_SCL
t_BUF
CONDITIONS
Hold Time, Repeated START
Condition
t_HD,STA
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Hold Time Slave
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of SDA and SCL,
Receiving
t_SU,STA
t_SU,STO
t_HD,DAT
t_HD,DAT
t_SU,DAT
t_LOW
t_HIGH
(Note 4)
(Note 4)
t_R
(Notes 2, 5)
Fall Time of SDA and SCL,
Receiving
t_F
(Notes 2, 5)
MIN TYP MAX UNITS
400
kHz
1.3
µs
0.6
µs
0.6
0.6
15
15
100
1.3
0.7
20 +
0.1C_B
20 +
0.1C_B
µs
µs
900
ns
900
ns
ns
µs
µs
300
ns
300
ns
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