MAX6650_14 Datasheet, PDF (3/25 Pages) Maxim Integrated Products – Fan-Speed Regulators and Monitors with SMBus/I2C-Compatible Interface

MAX6650/MAX6651
Fan-Speed Regulators and Monitors
with SMBus/I²C-Compatible Interface
ELECTRICAL CHARACTERISTICS (continued)
(V_CC = 3.0V to 5.5V, T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C and V_CC = 5V.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
ADDRESS SELECT (ADD)
ADD Input Low Voltage
V_IL(ADD) Selects slave address 90h (Table 1)
0.1
ADD Input High Voltage
V_IH(ADD) Selects slave address 96h (Table 1)
V_CC - 0.05
ADD Input Leakage
I_LADD Selects slave address 36h (Table 1) (Note 3)
-1
0
ADD External Pulldown Resistor
to GND
R_ADD
Selects slave address 3Eh (Table 1)
9.5
10.5
ADD Pulldown Current
I_ADD
SMBus/I²C INTERFACE (SDA, SCL)
Data Output Sink Current
I_SDA
Input Leakage Current
Input Low Voltage
V_IL
Input High Voltage
V_IH
Input Hysteresis
V_HYS
V_ADD = 0.5V (Note 4)
V_SDA = 0.6V
0 < V_IN < V_CC
V_CC ≤ 3.6V
V_CC > 3.6V
-80
-40
6
±1
0.8
2
3
200
UNITS
V
V
µA
kΩ
µA
mA
µA
V
V
mV
TIMING CHARACTERISTICS
(V_CC = 3.0V to 5.5V, T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C and V_CC = 5V.)
PARAMETER
SYMBOL
TACHOMETERS
Glitch Rejection
GPIO2 (Note 2)
Clock Frequency
f_CLK
Clock Frequency Uncertainty
f_CLK
SMBus/I²C INTERFACE (Figures 3, 4)
SCL Clock Frequency
f_SCL
Bus Free Time Between Stop
and Start Condition
t_BUF
CONDITIONS
Minimum pulse duration
V_CC = 5V
MIN TYP MAX
500
254
-10
+10
0
400
1.3
Hold-Time Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Data Setup Time
Rise-Time SDA/SCL Signal
(Receiving)
t_HD:STA
t_LOW
t_HIGH
t_HD:DAT
t_SU:DAT
(Note 5)
t_R
(Note 6)
0.6
1.3
0.6
0
900
100
20 + 0.1C_B(pF)
300
Fall-Time SDA/SCL Signal
(Receiving)
t_F
(Note 6)
20 + 0.1C_B(pF)
300
Fall-Time SDA Signal
(Transmitting)
t_F
I_SINK < 6mA (Note 6)
20 + 0.1C_B(pF)
250
UNITS
µs
kHz
%
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
Maxim Integrated
3