MAX3891 Datasheet, PDF (3/12 Pages) Maxim Integrated Products – 16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET with Clock Synthesis and LVPECL Inputs

16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET,
with Clock Synthesis and LVPECL Inputs
AC ELECTRICAL CHARACTERISTICS
(V_CC = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (V_CC - 2V), CML loads = 50Ω ±1% to V_CC, T_A = -40°C to +85°C. Typical values
are at T_A = +25°C and V_CC = +3.3V, unless otherwise noted.) (Note 1)
PARAMETER
Serial Clock Rate
Parallel Data Setup Time
Parallel Data-Hold Time
PCLKO to PCLKI Skew
SYMBOL
f_SCLK
t_SU
t_H
t_SKEW
(Notes 2, 3)
(Notes 2, 3)
Figure 1
CONDITIONS
MIN
300
700
0
TYP
2.488
MAX
+4.0
UNITS
GHz
ps
ps
ns
Output Jitter Generation
(SCLKO±)
Jitter bandwidth = 12kHz to 20MHz
3 ps_RMS
PECL Differential Output (SDO±,
SCLKO±) Rise/Fall Time
Parallel Input Clock Rate
Reference Clock Input (RCLK±)
Rise/Fall Time
t_R, t_F
f_PCLKI
t_R, t_F
20% to 80%
20% to 80%, f = 155.52MHz
155.52
120 ps
MHz
1.0 ns
Parallel Clock Output (PCLKO±)
Rise/Fall Time
t_R, t_F 20% to 80%
1.0 ns
Serial-Clock Output (SCLKO±)
to Serial-Data Output (SDO±)
t_SCLK-SD SCLKO rising edge to SDO edge
110
Delay
290 ps
Note 1: AC characteristics are guaranteed by design and characterization.
Note 2: Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel
clock with rise/fall time = 1ns (20% to 80%). See Figure 1.
Note 3: Setup and hold time measurements assume that the PCLKI and PDI signals are from the same source and have identical
common-mode voltages, swings, and slew rates.
(V_CC = +3.3V_, T_A = +25°C, unless otherwise noted.)
Typical Operating Characteristics
SUPPLY CURRENT vs. TEMPERATURE
200
180
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3891 toc02
SERIAL-DATA OUTPUT JITTER
MAX3891 toc03
f_RCLK = 155.52MHz
160
140
120
PECL OUTPUTS UNTERMINATED
100
-50 -25 0 25 50
75 100
TEMPERATURE (°C)
100ps/div
5000ps/div
TOTAL WIDEBAND RMS JITTER = 2.059ps,
PEAK-TO-PEAK JITTER = 16.70ps
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