MAX16824_09 Datasheet, PDF (3/13 Pages) Maxim Integrated Products – High-Voltage, Three-Channel Linear High-Brightness LED Drivers

High-Voltage, Three-Channel Linear
High-Brightness LED Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 12V, C_REG = 1µF to GND, I_REG = 0, R_{CS_} = 2Ω from CS_ to GND, T_J = T_A = -40°C to +125°C, unless otherwise noted. Typical
values are at T_J = T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
OUTPUTS (OUT1, OUT2, OUT3)
Turn-On Time
t_R
PWM_ rising time, t_R, is measured from 20%
to 80% of I_OUT
Turn-Off Time
t_F
PWM_ falling time, t_F, is measured from
80% to 20% of I_OUT
SPI INTERFACE (CLK, LE, OE, DIN, DOUT) (Figures 3 and 4)
DIN, CLK, LE, OE Input Bias
Current
V_DIN = V_CLK = V_LE = V_OE = 0 or 5V
DIN, CLK, LE, OE Input-Voltage
High
V_IH
2.2
DIN, CLK, LE, OE Input-Voltage
Low
V_IL
TYP MAX UNITS
1
µs
1
µs
1
µA
V
0.5
V
CLK Clock Period
t_CP
50% of CLK rising to 50% of next CLK
rising, Figure 3
50
ns
CLK Pulse-Width High
t_CH
50% of CLK rising to 50% of CLK falling,
Figure 3
24
ns
CLK Pulse-Width Low
t_CL
50% of CLK falling to 50% of CLK rising,
Figure 3
24
ns
DIN Setup Time
t_DS
50% of DIN rising to 50% of CLK rising,
Figure 3
5
ns
DIN Hold Time
t_DH
50% of CLK rising to 50% of DIN falling,
Figure 3
10
ns
DOUT Propagation Delay
t_DO
50% of CLK rising to 50% of DOUT rising/
falling, Figure 3
5
ns
DOUT Rise/Fall Time
DOUT Voltage High
DOUT Voltage Low
LE Pulse-Width High
t_DR/t_DF
C_DOUT = 10pF, 10% to 90% of DOUT
rising/falling edge (Note 6)
V_DOH I_SOURCE = 4mA
4.5
V_DOL I_SINK = 4mA
t_LW
50% of LE rising to 50% of LE falling,
Figure 3
20
15
ns
V
0.5
V
ns
LE Setup Time
t_LS
50% of CLK rising to 50% of LE rising,
Figure 3
15
ns
LE Rising to OUT_ Rising Delay
t_LRR
50% of LE rising to 50% of OUT_ rising,
Figure 4
150
ns
LE Rising to OUT_ Falling Delay
t_LRF
50% of LE rising to 50% of OUT_ falling,
Figure 4
475
ns
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