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MAX16008_11 Datasheet, PDF (3/13 Pages) Maxim Integrated Products – Low-Voltage, High-Accuracy, Quad Window Voltage Detectors in Thin QFN
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Low-Voltage, High-Accuracy, Quad Window
Voltage Detectors in Thin QFN
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.0V to 5.5V, TOL = GND, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.)
(Note 1)
PARAMETER
RESET Output-Voltage Low
RESET Output-Voltage High
SYMBOL
VOL
VOH
CONDITIONS
VCC = 3.3V, ISINK = 10mA, RESET asserted
VCC = 2.5V, ISINK = 6mA, RESET asserted
VCC = 1.2V, ISINK = 50µA, RESET asserted
VCC ≥ 2.0V, ISOURCE = 6µA, RESET
deasserted
MIN
0.8 x
VCC
TYP
MAX
0.30
0.30
0.30
UNITS
V
V
MR Input-Voltage Low
VIL
0.3 x
V
VCC
MR Input-Voltage High
MR Minimum Pulse Width
MR Glitch Rejection
MR to RESET Delay
MR Pullup Resistance
OUTPUTS (UVOUT_/OVOUT_)
UVOUT_, OVOUT_ Output-
Voltage Low
OVOUT_, OVOUT_ Output-
Voltage High
UVIN_/OVIN_ to UVOUT_/ OVOUT_
Propagation Delay
DIGITAL LOGIC
VIH
VOL
VOH
VCC = 3.3V, ISINK = 2mA
VCC = 2.5V, ISINK = 1.2mA
VCC ≥ 2.0V, ISOURCE = 6µA
tD
(VTH - 100mV) to (VTH + 100mV)
0.7 x
VCC
V
1
µs
100
ns
200
ns
12
20
28
kΩ
0.8 x
VCC
0.30
V
0.30
V
20
µs
TOL Input-Voltage Low
TOL Input-Voltage High
TOL Input Current
MARGIN Input-Voltage Low
VIL
VIH
TOL = VCC
VIL
0.7 x
VCC
0.3 x
V
VCC
V
100
nA
0.3 x
V
VCC
MARGIN Input-Voltage High
VIH
0.7 x
V
VCC
MARGIN Pullup Resistance
Pulled up to VCC
12
20
28
kΩ
MARGIN Delay Time
tMD Rising or falling (Note 5)
50
µs
Note 1: Devices are tested at TA = +25°C and guaranteed by design for TA = TMIN to TMAX.
Note 2: The outputs are guaranteed to be in the correct logic state down to VCC = 1V.
Note 3: Measured with MR and MARGIN unconnected.
Note 4: The minimum and maximum specifications for this parameter are guaranteed by using the worse case of the SRT current
and SRT threshold specifications. Do not set the reset timeout period to more than 1.12s.
Note 5: Amount of time required for logic to lock/unlock outputs from margin testing
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