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MAX1510_11 Datasheet, PDF (3/13 Pages) Maxim Integrated Products – Low-Voltage DDR Linear Regulator Thermal Fault Protection
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Low-Voltage DDR Linear Regulators
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TJ = TA = -40°C to +85°C for MAX1510ETB, TJ =
TA = -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
REFERENCE
REFIN Voltage Range
REFIN Input-Bias Current
REFIN Undervoltage-Lockout
Voltage
SYMBOL
CONDITIONS
VREFIN
IREFIN
TA = +25°C
Rising edge, hysteresis = 50mV
MIN TYP MAX UNITS
0.5
1.5
V
-1
+1
µA
0.35 0.45
V
REFOUT Voltage
REFOUT Load Regulation
FAULT DETECTION
Thermal-Shutdown Threshold
VCC Undervoltage-Lockout
Threshold
VREFOUT VCC = 3.3V, IREFOUT = 0V
ΔVREFOUT IREFOUT = ±5mA
TSHDN
VUVLO
Rising edge, hysteresis = 15°C
Rising edge, hysteresis = 100mV
VREFIN
- 0.01
VREFIN
VREFIN
+ 0.01
V
-20
+20
mV
+165
°C
2.45 2.55 2.65
V
IN Undervoltage-Lockout
Threshold
Rising edge, hysteresis = 55mV
0.9
1.1
V
Current-Limit Threshold
Soft-Start Current-Limit Time
INPUTS AND OUTPUTS
ILIMIT
tSS
TA = -40°C to +85°C
TA = -40°C to +125°C
1.8
3
4.2
A
1.5
3
4.2
200
µs
PGOOD Lower Trip Threshold
With respect to feedback threshold,
hysteresis = 12mV
-200 -150 -100
mV
PGOOD Upper Trip Threshold
With respect to feedback threshold,
hysteresis = 12mV
100
150
200
mV
PGOOD Propagation Delay
tPGOOD
OUTS forced 25mV beyond PGOOD trip
threshold
5
10
35
µs
PGOOD Startup Delay
PGOOD Output Low Voltage
PGOOD Leakage Current
SHDN Logic Input Threshold
SHDN Logic Input Current
Startup rising edge, OUTS within ±100mV of
the feedback threshold
1
2
3.5
ms
ISINK = 4mA
0.3
V
IPGOOD
OUTS = REFIN (PGOOD high impedance),
PGOOD = VCC + 0.3V, TA = +25°C
1
µA
Logic-high
2.0
V
Logic-low
0.8
SHDN = VCC or GND, TA = +25°C
-1
V
+1
µA
Note 1: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through cor-
relation using statistical-quality-control (SQC) methods.
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