MAX14840PMB1 Datasheet, PDF (3/7 Pages) Maxim Integrated Products – MAX14840PMB1 Peripheral Module

MAX14840PMB1 Peripheral Module
Connector JP1 (Termination Select)
This jumper port optionally inserts a 120I termination
resistor across the transmit-positive and negative nets.
The JP1 jumper should be installed at the endpoints of
the RS-485 network, and not at the midpoints.
Software and FPGA Code
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module functionality,
and which uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions within
a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download at
www.maxim-ic.com. Quick start instructions are also
available as a separate document.
J1
1
2
3
4
R1
150 RE
R2
150 DI
R3
150 RO
R4
150 DE
5
GND
6
VCC
VCC
VCC
C1
C2
1uF
0. 1uF
GND
GND
U1
1
RO
2
RE
3
DE
4
DI
VCC
B
A
GND
MAX14840E
8 _VCC
7
6
5 _GND
Figure 1. MAX14840PMB1 Peripheral Module Schematic
RS485-B
1
2
JP1
R5
120
RS485-A
J2
1_A
2_B
Figure 2. MAX14840PMB1 Peripheral Module Component Placement Guide—Component Side
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