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MAX1437 Datasheet, PDF (3/23 Pages) Maxim Integrated Products – Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1µF, CREFP to GND = 10µF,
CREFN to GND = 10µF, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
Total Harmonic Distortion
Intermodulation Distortion
Third-Order Intermodulation
Aperture Jitter
Aperture Delay
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
SYMBOL
CONDITIONS
THD
fIN = 5.3MHz at -0.5dBFS
fIN = 19.3MHz at -0.5dBFS
IMD
f1 = 5.3MHz at -6.5dBFS
f2 = 6.3MHz at -6.5dBFS
IM3
f1 = 5.3MHz at -6.5dBFS
f2 = 6.3MHz at -6.5dBFS
tAJ Figure 11
tAD Figure 11
SSBW Input at -20dBFS
LSBW Input at -0.5dBFS
IN_P = IN_N
Over-Range Recovery Time
tOR RS = 25Ω, CS = 50pF
INTERNAL REFERENCE
REFADJ Internal Reference-Mode
Enable Voltage
(Note 4)
REFADJ Low-Leakage Current
REFIO Output Voltage
Reference Temperature
Coefficient
VREFIO
TCREFIO
EXTERNAL REFERENCE
REFADJ External Reference-
Mode Enable Voltage
(Note 4)
REFADJ High-Leakage Current
REFIO Input Voltage
REFIO Input Voltage Tolerance
REFIO Input Current
IREFIO
COMMON-MODE OUTPUT (CMOUT)
CMOUT Output Voltage
CLOCK INPUT (CLK)
VCMOUT
Input High Voltage
VCLKH
Input Low Voltage
Clock Duty Cycle
Clock Duty-Cycle Tolerance
Input Leakage
Input Capacitance
VCLKL
DIIN
DCIN
Input at GND
Input at AVDD
MIN
TYP
MAX UNITS
-96
dBc
-90
-79
90.7
dBc
98.7
<0.4
1
100
100
0.44
1
dBc
psRMS
ns
MHz
MHz
LSBRMS
Clock
cycle
0.1
V
1.5
mA
1.18
1.24
1.30
V
120
ppm/°C
AVDD -
0.1V
V
200
µA
1.24
V
±5
%
<1
µA
0.76
V
0.8 x
CVDD
V
0.2 x
CVDD
V
50
%
±30
%
5
µA
80
5
pF
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