DS8500_09 Datasheet, PDF (3/7 Pages) Maxim Integrated Products – HART Modem

HART Modem
Pin Description
PIN
1, 2
3, 9, 16,
17, 18
4
5
6
7
8
10
11
12
13
14
15
19
20
—
NAME
DVDD Digital Supply Voltage
DGND Digital Ground
FUNCTION
RST
Active-Low Reset, Digital Input/Output. This pin includes an internal pullup resistor and is driven low
as an output when an internal reset condition occurs.
OCD
Carrier Detect, Digital Output. A logic-high indicates a valid carrier detection on FSK_IN.
OCD = 1 when FSK_IN amplitude is greater than 120mV_P-P.
OCD = 0 when FSK_IN amplitude is less than 80mV_P-P.
RTS
XTAL1
XTAL2
Request to Send, Digital Input. When set high, the device is put into the demodulator mode. A logic-low
puts the device into modulator mode.
Crystal Pin or Input for External Clock at 3.6864MHz
Crystal Pin or Output of the Crystal Amplifier
XCEN
External Clock Enable, Digital Input. When set high, this pin allows the user to drive an external clock
signal through XTAL1. When in this mode, XTAL2 should be left unconnected. An external crystal must
be connected between XTAL1 and XTAL2 when set low.
AVDD Analog Supply Voltage
FSK_OUT
FSK Out, Analog Output. Output of the modulator. Provides a phase-continuous, FSK-modulated output
signal (1200Hz and 2200Hz output frequencies) to the 4–20mA current loop interface circuit.
REF
Reference, Analog Output. The internal voltage reference is provided as output. This pin must be
connected to a 0.1μF capacitor.
FSK_IN
AGND
D_OUT
D_IN
EP
FSK In, Analog Input. Input for the FSK-modulated HART receive signal from the 4–20mA current loop
interface circuit.
Analog Ground
Digital Data Out, Digital Output. Output from the demodulator.
Digital Data In, Digital Input. Input to the modulator.
Exposed Pad. Should be connected to ground (DGND, AGND).
Block Diagram
RST
DVDD DGND AGND
AVDD
XTAL1
XTAL2
XCEN
OCD
D_OUT
RTS
D_IN
CRYSTAL
OSCILLATOR
CLOCK
GENERATOR
POWER
MONITOR
V_REF
1.23V
Rx
DEMODULATOR
Tx
MODULATOR
DIGITAL
FILTER
DS8500
SAMPLE/HOLD
ADC
DAC
REF
FSK_IN
FSK_OUT
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