DS75LX Datasheet, PDF (3/13 Pages) Maxim Integrated Products – Digital Thermometer and Thermostat with Extended Addressing

DS75LX: Digital Thermometer and Thermostat with Extended Addressing
SCL Frequency
f_SCL
AC ELECTRICAL CHARACTERISTICS (continued)
400
kHz
(1.7V ≤ V_DD ≤ 3.7V, T_A = -55°C to +125°C.)
PARAMETER
SYMBOL
CONDITIONS
Bus Free Time Between
a STOP and START
Condition
t_BUF
(Note 7)
START and Repeated
START Hold Time from
Falling SCL
t_HD:STA
(Notes 7, 8)
Low Period of SCL
t_LOW
(Note 7)
High Period of SCL
t_HIGH
(Note 7)
Repeated START
Condition Setup Time to
Rising SCL
t_SU:STA
(Note 7)
Data-Out Hold Time from
Falling SCL
t_HD:DAT
(Notes 7, 9)
Data-In Setup Time to
Rising SCL
t_SU:DAT
(Note 7)
Rise Time of SDA and
SCL (Receive)
t_R
(Notes 7, 10)
Fall Time of SDA and
SCL (Receive)
t_F
(Notes 7, 10)
Spike Suppression
Filter Time (Deglitch
t_SS
Filter)
STOP Setup Time to
Rising SCL
t_SU:STO
(Note 7)
Capacitive Load for Each
Bus Line
C_BB
Input Capacitance
C_I
Serial Interface Reset
Time
t_TIMEOUT
SDA time low
(Notes 11, 12)
MIN
TYP
MAX UNITS
1.3
µs
600
ns
1.3
µs
0.6
µs
600
ns
0
100
20 +
0.1C_BB
20 +
0.1C_BB
0
0.9
µs
ns
300
ns
300
ns
50
ns
600
ns
400
pF
5
pF
75
325
ms
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
V_DD must be decoupled with a high-quality 0.1µF bypass capacitor. X5R or X7R ceramic surface-mount capacitors are
recommended.
Internal heating caused by O.S. loading causes the DS75LX to read approximately 0.5°C higher if O.S. is sinking the max
rated current.
All voltages are referenced to ground.
I_DD specified with O.S. pin open and A0–A2 pins grounded.
I_DD and address leakage specified with V_DD at 3.0V and SDA, SCL = 3.0V at 0°C to +70°C.
Address pins A0, A1, A2 are directly connected to V_DD, V_SS, or floating with less than 50pF capacitive load.
See the timing diagram (Figure 1). All timing is referenced to 0.9 x V_DD and 0.1 x V_DD.
After this period, the first clock pulse is generated.
The DS75LX provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL's falling
edge.
For example, if C_B = 300pF, then t_R[min] = t_F[min] = 50ns.
This timeout applies only when the DS75LX is holding SDA low. Other devices can hold SDA low indefinitely and the DS75LX
will not reset.
The DS75LX is available with timeout feature disabled upon special order. Contact Factory.
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
SDA
Data Input/Output for 2-Wire Serial Communication Port (Open Drain)
2
SCL
Clock Input for 2-Wire Serial Communication Port
3
O.S.
Thermostat Output Open Drain
4
GND
Ground
5
A₂
Address Input
6
A₁
Address Input
7
A₀
Address Input
8
V_DD
Supply Voltage. +1.7V to +3.7V supply pin. V_DD must have an external bypass
capacitor to GND. 0.1µF X5R or X7R ceramic SMT caps recommended.
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