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DS4266 Datasheet, PDF (3/6 Pages) Maxim Integrated Products – DDR Clock Oscillator
DDR Clock Oscillator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
LVDS
Output High Voltage
Output Low Voltage
Differential Output Voltage
Output Common-Mode Voltage
Variation
SYMBOL
CONDITIONS
VOHLVDSO
VOLLVDSO
|VODLVDSO|
100 differential load (Note 1)
100 differential load (Note 1)
100 differential load
VLVDSOCOM 100 differential load
MIN TYP
0.925
250
Change in Differential Magnitude
or Complementary Inputs
|VODLVDSO|
100 differential load
Offset Output Voltage
Differential Output Impedance
VOFFLVDSO
ROLVDSO
100 differential load (Note 1)
1.125
80
Output Current
LVSSLVDSO
OUTN or OUTP shorted to ground and
measure the current in the shorting path
Output Rise Time (Differential)
Output Fall Time (Differential)
Duty Cycle
LLVDSO
tRLVDSO
tFLVDSO
DCYCLE_LVDS
OUTN or OUTP shorted together
20% to 80%
80% to 20%
6.5
175
175
48
Propagation Delay from OE Going
Low to Logical 1 at OUTP
tPA1
Propagation Delay from OE Going
High to Output Active
tP1A
LVPECL
Output High Voltage
VOH
Output connected to 50 at PECL_BIAS
at VCC - 2.0V
Output Low Voltage
VOL
Output connected to 50 at PECL_BIAS
at VCC - 2.0V
Differential Voltage
Rise Time
Fall Time
Duty Cycle
VDIFF_PECL
tR-PECL
tF-PECL
DCYCLE_PECL
Output connected to 50 at PECL_BIAS
at VCC - 2.0V
Propagation Delay from OE Going
Low to Output High Impedance
tPAZ
VCC -
1.085
VCC -
1.825
0.595
48
0.710
200
200
Propagation Delay from OE Going
High to Output Active
tPZA
Note 1: All voltages referenced to ground.
Note 2: AC parameters are guaranteed by design and not production tested.
Note 3: Frequency stability is calculated as: ΔfTOTAL = ΔfTEMP + ΔfVCC x (3.3 x 5%) + ΔfLOAD + ΔfAGING.
MAX UNITS
1.475
V
V
425
mV
150
mV
25
mV
1.275
V
140

40
mA
ps
ps
52
%
200
ns
200
ns
VCC -
V
0.88
VCC -
V
1.62
V
ps
ps
52
%
200
ns
200
ns
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