DS28E01-100 Datasheet, PDF (3/21 Pages) Dallas Semiconductor – 1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

ABRIDGED DATA SHEET
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
ELECTRICAL CHARACTERISTICS (continued)
(T_A = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 16, 17)
Standard speed
60
t_W0L Overdrive speed, V_PUP > 4.5V
5
Overdrive speed
6
Write-One Low Time
(Notes 2, 17)
Standard speed
t_W1L
Overdrive speed
1
1
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 18)
Standard speed
t_RL
Overdrive speed
5
1
Read Sample Time
(Notes 2, 18)
EEPROM
t_MSR
Standard speed
Overdrive speed
t_RL + 
t_RL + 
Programming Current
Programming Time
Write/Erase Cycles (Endurance)
(Notes 21, 22)
I_PROG
t_PROG
N_CY
(Notes 5, 19)
(Note 20)
At +25°C
At +85°C (worst case)
200k
50k
Data Retention
(Notes 23, 24, 25)
t_DR
At +85°C (worst case)
40
SHA-1 ENGINE
Computation Current
Computation Time
(Notes 5, 26)
I_LCSHA
t_CSHA
Refer to the full data sheet.
MAX UNITS
120
15.5
µs
15.5
15
µs
2
15 - 
µs
2-
15
µs
2
0.8
mA
10
ms

Years
mA
ms
Note 1: Limits are 100% production tested at T_A = +25°C and/or T_A = +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4: Maximum value represents the internal parasite capacitance when V_PUP is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6: V_TL, V_TH, and V_HY are a function of the internal supply voltage, which is a function of V_PUP, R_PUP, 1-Wire timing, and
capacitive loading on IO. Lower V_PUP, higher R_PUP, shorter t_REC, and heavier capacitive loading all lead to lower values of
V_TL, V_TH, and V_HY.
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to V_ILMAX at all times the master is driving IO to a logic 0 level.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After V_TH is crossed during a rising edge on IO, the voltage on IO must drop by at least V_HY to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at t_REH after V_TH has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to t_W0LMIN + t_RECMIN.
Note 15: Interval after t_RSTL during which a bus master can read a logic 0 on IO if there is a DS28E01-100 present. The first presence
pulse after power-up could be outside this interval but will be complete within 2ms after power-up.
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table.
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