DS1341_12 Datasheet, PDF (3/16 Pages) Maxim Integrated Products – Low-Current I2C RTCs for High-ESR Crystals

Low-Current I²C RTCs for High-ESR Crystals
AC ELECTRICAL CHARACTERISTICS
(VCC = +1.8V to +5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Note 2, Figure 1)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
SYMBOL
fSCL (Note 6)
tBUF
CONDITIONS
Hold Time (Repeated) START
Condition
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time
Data Setup Time
Setup Time for a Repeated
START Condition
tHD:STA (Note 7)
tLOW
tHIGH
tHD:DAT
tSU:DAT
(Notes 8, 9)
(Note 10)
tSU:STA
Rise Time of Both SDA and SCL
Signals
tR
(Note 11)
Fall Time for Both SDA and SCL
Signals
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line
I/O Capacitance
SCL Spike Suppression
Oscillator Stop Flag (OSF) Delay
Timeout Interval
tF
(Note 11)
tSU:STO
CB
(Note 11)
CI/O
tSP
tOSF
tTIMEOUT
(Note 12)
(Note 12)
(Note 13)
(Note 14)
MIN TYP MAX UNITS
400
kHz
1.3
Fs
0.6
Fs
1.3
Fs
0.6
Fs
0
0.9
Fs
100
ns
0.6
Fs
20 +
0.1CB
20 +
0.1CB
0.6
300
ns
300
ns
Fs
400
pF
10
pF
30
ns
25
100
ms
25
35
ms
CRYSTAL PARAMETERS
PARAMETER
Nominal Frequency
Series Resistance
Load Capacitance
SYMBOL
fO
ESR
CL
DS1341
DS1342
CONDITIONS
MIN TYP MAX UNITS
32.768
kHz
100
kI
6
pF
12.5
Note 2: Limits at -40NC are guaranteed by design; not production tested.
Note 3: Voltage referenced to ground.
Note 4: Specified with I²C bus inactive. Oscillator operational, INTCN = 1, ECLK = 0.
Note 5: Applies to CLKIN/INTA and SQW/INTB only.
Note 6: The minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if SCL is
held low for tTIMEOUT.
Note 7: After this period, the first clock pulse is generated.
Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 9: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT R to 250ns must then be
met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 =
1250ns before the SCL line is released.
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