DS1307_06 Datasheet, PDF (3/15 Pages) Maxim Integrated Products – 64 x 8, Serial, I2C Real-Time Clock

DS1307 64 x 8, Serial, I²C Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(V_CC = 4.5V to 5.5V; T_A = 0°C to +70°C, T_A = -40°C to +85°C.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
SYMBOL
f_SCL
t_BUF
CONDITIONS
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_R
(Note 4)
(Notes 5, 6)
t_F
t_SU:STO
MIN
0
4.7
4.0
4.7
4.0
4.7
0
250
TYP
MAX
100
UNITS
kHz
µs
µs
µs
µs
µs
µs
ns
1000
ns
300
ns
4.7
µs
CAPACITANCE
(T_A = +25°C)
PARAMETER
Pin Capacitance (SDA, SCL)
Capacitance Load for Each Bus
Line
SYMBOL CONDITIONS
C_I/O
C_B
(Note 7)
MIN
TYP
MAX UNITS
10
pF
400
pF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
All voltages are referenced to ground.
Limits at -40°C are guaranteed by design and are not production tested.
I_CCS specified with V_CC = 5.0V and SDA, SCL = 5.0V.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V_IH(MIN) of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum t_HD:DAT only has to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.
C_B—total capacitance of one bus line in pF.
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