MAXQ612_11 Datasheet, PDF (29/35 Pages) Maxim Integrated Products – 16-Bit Microcontrollers with Infrared Module and Optional USB

16-Bit Microcontrollers with
Infrared Module and Optional USB
Table 4. Power-Fail Warning Level Selection
PWCN.PFWARNCN[1:0]
00
01
10
11
PFW THRESHOLD
(V)
1.8
1.9
2.55
2.75
mode to minimize power consumption. This feature is
enabled using the power-fail monitor disable (PFD) bit
in the PWCN register. The reset default state for the PFD
bit is 1, which disables the power-fail monitor function
during stop mode. If power-fail monitoring is disabled
(PFD = 1) during stop mode, the circuitry responsible
for generating a power-fail warning or reset is shut down
and neither condition is detected. Thus, the VDD < VRST
condition does not invoke a reset state. However, in the
event that VDD falls below the POR level, a POR is gen-
erated. The power-fail monitor is enabled prior to stop
mode exit and before code execution begins. If a power-
fail warning condition (VDD < VPFW) is then detected,
the power-fail interrupt flag is set on stop mode exit. If a
power-fail reset condition is detected (VDD < VRST), the
CPU goes into reset.
Power-Fail Warning
The power-fail monitor can assert an interrupt if the volt-
age falls below a configurable threshold between the
operating voltage and the reset voltage. This, if enabled,
can allow the firmware to perform housekeeping tasks if
the voltage level decays below the warning threshold.
The power-fail threshold value should only be changed
when the power-fail warning interrupt is disabled (CKCN.
PFIE = 0) to prevent unintended triggering of the power-
fail warning condition.
The power-fail warning threshold is reset to 1.8V by a
POR and is not affected by other resets. See Table 4.
Power-Fail Detection
Figures 5, 6, and 7 show the power-fail detection and
response during normal and stop-mode operation.
If a reset is caused by a power-fail, the power-fail monitor
can be set to one of the following intervals:
• Always on—continuous monitoring
• 2¹¹ nanopower ring oscillator clocks (~256ms)
• 2¹² nanopower ring oscillator clocks (~512ms)
• 2¹³ nanopower ring oscillator clocks (~1.024s)
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
V_DD
C
V_PFW
V_RST
B
V_POR
A
t < t_PFW
D
t ≥ t_PFW
E
t ≥ t_PFW
F
t ≥ t_PFW
G
H
I
INTERNAL RESET
(ACTIVE HIGH)
Figure 5. Power-Fail Detection During Normal Operation
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