MAX9257A Datasheet, PDF(26/53 Page) Maxim Integrated Products – Fully Programmable Serializer/Deserializer with UART/I2C Control Channel

◁

MAX9257A/MAX9258A

Fully Programmable Serializer/Deserializer

with UART/I2C Control Channel

Table 11. Format for 18-Bit Serial-Word Length with Parity (Parallel-Word Width = 14)

BIT 1 2

7 8 9 10 11 12 13 14 15 16 17 18

NAME PR PRB EN0 EN1 HSYNC VSYNC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

Table 12. Format for 16-Bit Serial-Word Length with Parity (Parallel-Word Width = 12)

BIT 1 2

9 10 11 12 13 14 15 16

NAME PR PRB EN0 EN1 HSYNC VSYNC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Table 13. Format for 14-Bit Serial-Word Length with Parity (Parallel-Word Width = 10)

BIT 1 2

NAME PR PRB EN0 EN1 HSYNC VSYNC D0

LVDS Serial Data

Serial LVDS data is transmitted least significant bit (LSB)

to most significant bit (MSB) as shown in Tables 5 through

13. The ECU at startup can program the parallel word

width, serial frequency range, parity, spread-specÂtrum,

and pixel clock frequency range (see the MAX9257A

Pixel Clock Frequency Range

The devices each have registers that can be configured

at startup. Depending on the word length, the MAX9257A

multiplies PCLK_IN (pixel clock) by 12, 14, 16, 18, or

20 using an internal PLL to generÂate the serial clock.

Use Table 20 for proper selection of available PCLK fre-

quency and serial-data ranges. Parallel data is serialized

using the serial-clock and serialized bits are transmitted

at the MAX9257A LVDS outputs. The devices support

a wide range for PCLK_IN (Table 14). If the pixel clock

frequency needs to change to a frequency outside the

proÂgrammed range, the ECU must program both the

MAX9257A and the MAX9258A in the same control chanÂ

nel session.

Serial-Data Rate Range

The word length and pixel clock is limited by the maxiÂ

mum serial-data rate of 840Mbps. The following formula

shows the relation between word length, pixel clock, and

serial clock:

Serial-word length x pixel clock = serial-data rate =

840Mbps

For example, if PCLK_IN is 70MHz, the serial-word length

has to be 12 bits including DC balance bits if parity is not

enabled to keep the serial-data rate under 840Mbps. If

Table 14. MAX9257A Pixel Clock Range

(PCLK_IN)

FREQUENCY (MHz)

5â10

10â20

20â40

40â70

PRATE (REG0[7:6])

Table 15. Serial-Data Rate Range

SERIAL-DATA RATE (Mbps)

60â100

100â200

200â400

400â840

SRATE (REG0[5:4])

the serial-word length is 20 bits, the maximÂ um PCLK_IN

frequency is 42MHz. The serial-data rate can vary from

60Mbps to 840Mbps and can be programmed at power-

up (Table 15). Use Table 20 for proper selection of avail-

able PCLK frequency and serial data ranges. Operating

in the incorrect range for either the serial-data rate or

PCLK_IN can result in excessive current dissipation and

failure of the MAX9258A to lock to the MAX9257A.

LVDS Common-Mode Bias

The output common-mode bias is 1.2V at the LVDS

inputs on the MAX9258A and LVDS outputs on the

MAX9257A. No external resistors are required to provide

bias for AC-coupling the LVDS inputs and outputs.

▷