DS31256 Datasheet, PDF (25/183 Pages) Maxim Integrated Products – 256-Channel, High-Throughput HDLC Controller

DS31256 256-Channel, High-Throughput HDLC Controller
Signal Name:
PINTA
Signal Description: PCI Interrupt
Signal Type:
Output (open drain)
This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from
the device driver. PINTA is deasserted when the device-interrupting source has been serviced or masked. This
signal is updated on the rising edge of PCLK.
3.6 PCI Extension Signals
These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the
DS31256 is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a
non-PCI environment like an Intel i960-type bus.
Signal Name:
PXAS
Signal Description: PCI Extension Address Strobe
Signal Type:
Output
This active-low signal is asserted low on the same clock edge as PFRAME and is deasserted after one clock
period. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the
rising edge of PCLK.
Signal Name:
PXDS
Signal Description: PCI Extension Data Strobe
Signal Type:
Output
This active-low signal is asserted when the PCI bus either contains valid data to be read from the device or can
accept valid data that is written into the device. This signal is only asserted when the device is an initiator. This
signal is an output and is updated on the rising edge of PCLK.
Signal Name:
PXBLAST
Signal Description: PCI Extension Burst Last
Signal Type:
Output
This active-low signal is asserted on the same clock edge as PFRAME is deasserted and is deasserted on the same
clock edge as PIRDY is deasserted. This signal is only asserted when the device is an initiator. This signal is an
output and is updated on the rising edge of PCLK.
3.7 Supply and Test Signal Description
Signal Name:
TEST
Signal Description: Factory Test Input
Signal Type:
Input (with internal 10kΩ pullup)
This input should be left open-circuited by the user.
Signal Name:
Signal Description:
V_DD
Positive Supply
Signal Type:
n/a
3.3V (±10%). All V_DD signals should be connected together.
Signal Name:
V_SS
Signal Description: Ground Reference
Signal Type:
n/a
All V_SS signals should be connected to the local ground plane.
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