MAXQ3180 Datasheet, PDF (24/48 Pages) Maxim Integrated Products – Low-Power, Multifunction, Polyphase AFE

Low-Power, Multifunction, Polyphase AFE
Table 4. RAM Register Summary (continued)
NAME
ADDRESS
(BYTE)
DESCRIPTION
R/W
DEFAULT
VALUE
(HEX)
REV_TIMO
124
0x07C
Reverse Pulse
Direction
R/W
Timeout
0x000B
ACC_TIMO
126
0x07E
Energy
Accumulation R/W
Delay Timeout
0x0032
COM_TIMO
128
0x080
Communication _R/W
Timeout
0x03E8
R_ACFG
130
0x082
Analog Control
Shadow
R/W
0x0007
R_ADCRATE
132
0x084
Analog Control
Shadow
R/W
0x00C7
R_ADCACQ
134
0x086
Analog Control
Shadow
R/W
0x002F
R_SPICF
136
0x088
SPI Control
Shadow
R/W
0x0080
BITS
NAME
DESCRIPTION
15:0
Number of line cycles to detect
reverse pulse direction
15:0
Number of line cycles before
starting energy accumulation
15:0
Number of frames to reset
communication channel
15:8
—
These bits are reserved and
should be set to 0
7
ADCASD Automatic shutdown disable
6
ADCRY Sample ready (system)
ADC clock divider
00: ADC = SYSCLK
5:4
ADCCD _{01: ADC = SYSCLK/2}
[1:0]
10: ADC = SYSCLK/4
11: Reserved
3
2
1
0
15:9
8:0
15:7
6:0
15:8, 5:3
7
6
ADCBY ADC busy (system)
ADCIE ADC interrupt enable (system)
ARBE Internal V_REF enable
ADCE ADC enable
—
Reserved. Should be set to 0.
R_ADCRATE
Number of SYSCLKs between
two consecutive ADC
[8:0]
conversions minus 1
—
Reserved. Should be set to 0.
Number of SYSCLKs for amplifier
R_ADCACQ
[6:0]
to acquire input signal before
conversion minus 1
—
Reserved. Should be set to 0.
ESPII SPI interrupt enable (system)
SSEL active level select
SAS
0: SSEL active low
1: SSEL active high
5:3
—
These bits are reserved and
should be set to 0
SPI character length bit
2
CHR
0: 8 bits
1: 16 bits
1
CKPHA SPI clock phase select
0
CKPOL SPI clock polarity select
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