MAX5952_10 Datasheet, PDF (24/50 Pages) Maxim Integrated Products – High-Power, Quad, PSE Controller for Power-Over-Ethernet

High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Slave Address
The MAX5952 has a 7-bit long slave address (Figure
9). The bit following the 7-bit slave address (bit eight) is
the R/W bit, which is low for a write command and high
for a read command.
010 always represents the first three bits (MSBs) of the
MAX5952 slave address. Slave address bits A3, A2,
A1, and A0 represent the states of the MAX5952’s A3,
A2, A1, and A0 inputs, allowing up to sixteen MAX5952
devices to share the bus. The states of the A3, A2, A1
and A0 latch in upon the reset of the MAX5952 into reg-
ister R11h. The MAX5952 monitors the bus continuous-
ly, waiting for a START condition followed by the
MAX5952’s slave address. When a MAX5952 recog-
nizes its slave address, the MAX5952 acknowledges
and is then ready for continued communication.
Global Addressing and Alert Response Protocol
The global address call is used in writing mode to write
the same register to multiple devices (address 0x60). In
read mode (address 0x61), the global address call is
used as the alert response address. When responding
to a global call, the MAX5952 puts out on the data line
its own address whenever its interrupt is active. So
does every other device connected to the SDAOUT line
that has an active interrupt. After every bit transmitted,
the MAX5952 checks that the data line effectively cor-
responds to the data it is delivering. If it is not, it then
backs off and frees the data line. This litigation protocol
always allows the part with the lowest address to com-
plete the transmission. The microcontroller can then
respond to the interrupt and take proper actions. The
MAX5952 does not reset its own interrupt at the end of
the alert response protocol. The microcontroller has to
do it by clearing the event register through their CoR
adresses or activating the CLR_INT pushbutton.
Message Format for Writing to the MAX5952
A write to the MAX5952 comprises of the MAX5952’s
slave address transmission with the R/W bit set to 0, fol-
lowed by at least one byte of information. The first byte
of information is the command byte (Figure 10). The
command byte determines which register of the
MAX5952 is written to by the next byte, if received. If
the MAX5952 detects a STOP condition after receiving
the command byte, the MAX5952 takes no further
action beyond storing the command byte. Any bytes
received after the command byte are data bytes. The
first data byte goes into the internal register of the
MAX5952 selected by the command byte. If the
MAX5952 transmits multiple data bytes before the
MAX5952 detects a STOP condition, these bytes store
in subsequent MAX5952 internal registers because the
control byte address auto-increments.
MSB
SDA ⁰
1
SCL
Figure 9. Slave Address
LSB
0
A3
A2
A1
A0
R/W
ACK
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION
ACKNOWLEDGE FROM MAX5952
D15 D14 D13 D12 D11 D10 D9 D8
S
SLAVE ADDRESS
0A
CONTROL BYTE
AP
R/W
ACKNOWLEDGE FROM MAX5952
Figure 10. Control Byte Received
24 ______________________________________________________________________________________