MAX19517 Datasheet, PDF (24/35 Pages) Maxim Integrated Products – Dual-Channel, 10-Bit, 130Msps ADC

Dual-Channel, 10-Bit, 130Msps ADC
CLK+
AVDD
5kΩ
10kΩ
100Ω
TERMINATION
(PROGRAMMABLE)
50Ω
2:1 MUX
20kΩ
50Ω
5kΩ
GND
CLK-
SELF-BIAS TURNED OFF FOR
SINGLE-ENDED CLOCK
OR POWER-DOWN.
SELECT
THRESHOLD
Figure 8. Simplified Clock Input Schematic
Clock Inputs
The input clock interface provides for flexibility in the
requirements of the clock driver. The MAX19517 accepts
a fully differential clock or single-ended logic-level clock.
For differential clock operation, connect a differential
clock to the CLK+ and CLK- inputs. In this mode, the
input common mode is established internally to allow for
AC-coupling. The differential clock signal can also be
DC-coupled if the common mode is constrained to the
specified 1V to 1.4V clock input common-mode range.
For single-ended operation, connect CLK- to GND and
drive the CLK+ input with a logic-level signal. When the
CLK- input is grounded (or pulled below the threshold of
the clock mode detection comparator) the differential-to-
single-ended conversion stage is disabled and the logic-
level inverter path is activated.
Clock Divider
The MAX19517 offers a clock-divider option. Enable
clock division either by setting DIV0 and DIV1 through
the serial interface; see the Clock Divide/Data
SAMPLING
INSTANT
DUAL-BUS OUTPUT MODE
SAMPLING
SAMPLING
INSTANT
SAMPLING
t_AD
INSTANT
INSTANT
SAMPLING
SAMPLING
INSTANT
IN_
INSTANT
SAMPLE CLOCK
t_CLK
SAMPLE ON RISING EDGE
t_CH
t_CL
n
n+1
n+2
n+3
n+4
n+5
t_DD
DATA, DOR
n-10
n-9
n-8
n-7
n-6
n-5
n-4
t_DC
t_HOLD
t_SETUP
DCLK
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
Figure 9. Dual-Bus Output Mode Timing
24 ______________________________________________________________________________________