MAX16818 Datasheet, PDF (24/26 Pages) Maxim Integrated Products – 1.5MHz, 30A High-Efficiency, LED Driver with Rapid LED Current Pulsing

1.5MHz, 30A High-Efficiency, LED Driver
with Rapid LED Current Pulsing
Power Dissipation
The TQFN is a thermally enhanced package and can dis-
sipate about 2.7W. The high-power package makes the
high-frequency, high-current LED driver possible to oper-
ate from a 12V or 24V bus. Calculate power dissipation in
the MAX16818 as a product of the input voltage and the
total V_CC regulator output current (I_CC). I_CC includes qui-
escent current (I_Q) and gate drive current (I_DD):
P_D = V_IN x I_CC
[ ] ^ICC ^{= I}Q ^{+ f}SW ^{x (Q}G1 ^{+ Q}G2⁾
where Q_G1 and Q_G2 are the total gate charge of the low-
side and high-side external MOSFETs at V_GATE = 5V, I_Q
is estimated from the Supply Current (I_Q) vs. Frequency
graph in the Typical Operating Characteristics, and f_SW
is the switching frequency of the LED driver. For boost
drivers, only consider one gate charge, Q_G1.
Use the following equation to calculate the maximum
power dissipation (P_DMAX) in the chip at a given ambi-
ent temperature (T_A):
P_DMAX = 34.5 x (150 - T_A) mW.
PCB Layout Guidelines
Use the following guidelines to layout the switching
voltage regulator:
1) Place the IN, V_CC, and V_DD bypass capacitors
close to the MAX16818.
2) Minimize the area and length of the high current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
3) Keep short the current loop formed by the lower
switching MOSFET, inductor, and output capacitor.
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PCB.
5) Keep the SGND and PGND isolated and connect
them at one single point.
6) Run the current-sense lines CSP and CSN very
close to each other to minimize the loop area.
Similarly, run the remote voltage-sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
7) Avoid long traces between the V_DD bypass capaci-
tors, the driver output of the MAX16818, the MOS-
FET gates, and PGND. Minimize the loop formed by
the V_CC bypass capacitors, bootstrap diode, boot-
strap capacitor, the MAX16818, and the upper
MOSFET gate.
8) Distribute the power components evenly across the
board for proper heat dissipation.
9) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
10) Use wide copper traces (2oz) to keep trace induc-
tance and resistance low to maximize efficiency.
Wide traces also cool heat-generating components.
Pin Configuration
TOP VIEW
21 20 19 18 17 16 15
SGND 22
SENSE- 23
SENSE+ 24
SGND ²⁵
IN 26
MAX16818
V_CC 27
V_DD 28
* EXPOSED PAD
+
12 34 5 67
14 LIM
13 V_IOUT
12 RT/SYNC
11 EN
10 PGOOD
9 CLKOUT
8 SGND
TQFN
Chip Information
TRANSISTOR COUNT: 5654
PROCESS: BiCMOS
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