MAX32625 Datasheet, PDF (23/27 Pages) Maxim Integrated Products – High-Efficiency Microcontroller for Wearable Devices

MAX32625/MAX32626
Ultra-Low Power, High-Performance
ARM Cortex-M4F Microcontroller for Wearables
I²C Master and Slave
The I²C interface is a bidirectional, two-wire serial bus
that provides a medium-speed communications network.
It can operate as a one-to-one, one-to-many, or many-to-
many communications medium.
Two I²C interfaces allow combinations of up to two I²C
master engines and/or one I²C-selectable slave engine to
connect to a wide variety of I²C-compatible peripherals.
These engines support both standard-mode and fast-
mode I²C standards. The slave engine shares the same
I/O port as the master engines and is selected through
the I/O configuration settings. It provides the following
features:
●● Master or slave mode operation
●● Supports standard (7-bit) addressing or 10-bit
addressing
●● Support for clock stretching to allow slower slave
devices to operate on higher speed busses
●● Multiple transfer rates
• Standard mode: 100kbps
• Fast mode: 400kbps
●● Internal filter to reject noise spikes
●● Receiver FIFO depth of 16 bytes
●● Transmitter FIFO depth of 16 bytes
SPI (Master)
The SPI master-mode-only (SPIM) interface operates
independently in a single or multiple slave system and is
fully accessible to the user application.
The SPI ports provide a highly configurable, flexible, and
efficient interface to communicate with a wide variety of
SPI slave devices. The three SPI master ports (SPI0,
SPI1, SPI2) support the following features:
●● Supports all four SPI modes (0, 1, 2, 3) for single-bit
communication
●● High-speed AHB access to transmit and receive
using 32-byte Rx FIFO and 16-byte Tx FIFO
●● 3- or 4-wire mode for single-bit slave device
communication
●● Full-duplex operation in single-bit, 4-wire mode
●● Dual and quad I/O supported
●● Up to 5 slave select lines per port
●● Up to 2 slave ready lines
●● Programmable interface timing
●● Programmable SCK frequency and duty cycle
●● Programmable SCK alternate timing
●● SS assertion and deassertion timing with respect to
leading/trailing SCK edge
SPI (Slave)
The SPI slave (SPIS) port provides a highly configurable,
flexible, and efficient interface to communicate with a wide
variety of SPI master devices. The SPI slave interface
provides the following features:
●● Supports SPI modes 0 and 3
●● Full-duplex operation in single-bit, 4-wire mode
●● Slave select polarity fixed (active low)
●● Dual and quad I/O supported
●● High-speed AHB access to transmit and receive
using 32-byte FIFOs
●● Four interrupts to monitor FIFO levels
SPI (Execute in Place (SPIX) Master)
The SPI execute in place (SPIX) master allows the CPU
to transparently execute instructions stored in an external
SPI flash. Instructions fetched through the SPIX master
are cached just like instructions fetched from internal
program memory. The SPIX master can also be used to
access large amounts of external static data that would
otherwise reside in internal data memory.
UART
All three universal asynchronous receiver-transmitter
(UART) interfaces support full-duplex asynchronous
communication with optional hardware flow control (HFC)
modes to prevent data overruns. If HFC mode is enabled
on a given port, the system uses two extra pins to
implement the industry standard request to send (RTS)
and clear to send (CTS) methodology. Each UART is
individually programmable.
●● 2-wire interface or 4-wire interface with flow control
●● 32-byte send/receive FIFO
●● Full-duplex operation for asynchronous data transfers
●● Programmable interrupt for receive and transmit
●● Independent baud-rate generator
●● Programmable 9th bit supports even/odd parity or
multi-drop mode
●● User-selectable UART slave address
●● Start/stop bit support
●● Hardware flow control using RTS/CTS
●● Maximum baud rate: 1843.2 kB
www.maximintegrated.com
Maxim Integrated │  23